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參數(shù)資料
| 型號(hào)： | LSIFC909 |
| 英文描述： | LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00 |
| 中文描述： | LSIFC909光纖通道I / O處理器技術(shù)手冊(cè)2.1 8 / 00 |
| 文件頁(yè)數(shù)： | 61/144頁(yè) |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC909 |
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PCI Cache Mode
5-5
The PCI configuration
Command
register, bit 4 must be set.
The
Cache Line Size
register must contain a legal burst size (2, 4,
8, 16, 32, 64, or 128) value.
The chip must have enough bytes in the DMA FIFO to complete at
least one full cache line burst.
The chip must be aligned to a cache line boundary.
When these conditions have been met, the LSIFC909 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
5.3.3.2 Multiple Cache Line Transfers
The Write and Invalidate command can write multiple cache lines of data
in a single bus ownership. The chip issues a burst transfer as soon as it
reaches a cache line boundary. The size of the transfer is not
automatically the cache line size, but rather a multiple of the cache line
size as allowed for in Revision 2.1 of the PCI specification. The logic
selects the largest multiple of the cache line size based on the amount
of data to transfer.
When the DMA buffer contains less data than the value specified in the
Cache Line Size
register, the LSIFC909 throttles back to a Memory Write
command on the next cache line boundary.
5.3.3.3 Latency
In accordance with the PCI specification, the chip's latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out has occurred, the LSIFC909 continues to transfer up
until a cache line boundary. At that point, the chip relinquishes the bus,
and finishes the transfer at a later time using another bus ownership. If
the chip is transferring multiple cache lines it continues to transfer until
the next cache boundary is reached.
5.3.3.4 PCI Target Retry
During a Write and Invalidate transfer, if the target device issues a retry
(STOP with no TRDY, indicating that no data was transferred), the
LSIFC909 relinquishes the bus and immediately tries to finish the
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| LSIFC919-329BGA | 制造商:LSI Corporation 功能描述:Fiber Controller 329-Pin BGA |
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| LSIFC929-329BGA | 制造商:LSI Corporation 功能描述:Fiber Controller 456-Pin BGA |
| LSIFC929X | 制造商:LSI Corporation 功能描述:- Bulk |
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