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參數(shù)資料
| 型號(hào)： | IXF1010 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552 |
| 文件頁(yè)數(shù)： | 63/116頁(yè) |
| 文件大?。?/td> | 1392K |
| 代理商： | IXF1010 |
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IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
50
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
4.0
Applications
4.1
TX and RX FIFO Operation
4.1.1
TX FIFO
The IXF1010’s TX FIFOs are implemented with 4.5 KB for each channel. This provides enough
space for at least one maximum size packet per port storage and ensures that no under-run
conditions occur, assuming that the sending device can supply data at the required data rate.
The MAC threshold parameter, which is user programmable, determines when data is transmitted
out of the MAC. This parameter is configurable for specific block sizes and the user must ensure
that an under-run does not occur. The threshold must be set to a value that exceeds the programmed
MaxBurst1 parameter. This method of operation eliminates the possibility of under-run, except
when the controlling switch device fails.
4.1.2
RX FIFO
The IXF1010 RX FIFOs are provisioned so that each port has its own 17.0 KB memory space. This
is enough memory to ensure that there is never an over-run on any channel while transferring
normal Ethernet frame size data.
The FIFOs automatically generate Pause control frames to halt the link partner when the High
watermark is reached and to restart the link partner when the data stored in the FIFO falls below the
Low-watermark.
4.2
Reset and Initialization
When powering up the IXF1010, the hardware reset signal, Sys_Res, should be held active low for
a minimum of 100 ns after all of the power rails have fully stabilized to their nominal values and
the input clocks have reached their nominal frequency (TDCLK = 400 MHz, CLK125 = 125 MHz,
and CLK50 = 50 MHz).
Note:
In systems where the Sys_Res pin is driven from a single board-wide reset signal, the switch or
network processor will only come out of reset at the same time as the IXF1010, or possibly later.
This means that the TDCLK will not be stable when the Sys_Res pin is released. In the IXF1010, a
built-in feature reactivates the internal reset once TDCLK is applied. It is essential in this case to
ensure that the switch or network processor does not output TDCLK until it is stable and has
reached its nominal operating frequency.
The IXF1010 extends this hardware reset internally to ensure synchronization of all internal blocks
within the system. The internal reset is extended for a minimum of 220
s after all clocks are
stable. Before attempting to access the internal register set via the CPU interface allow for a
minimum of 500
s from all clocks being stable.
At this point, the device is correctly initialized and ready to be used. Clocks start to appear at the
relevant device ports and the SPI4-2 interface begins to source a training pattern on the receive side
while waiting for a training pattern on the transmit side. The SPI4-2 interface syncs up with the
connected switch or network processor per the SPI4-2 Specification.
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| IXF102A | 功能描述:IRIX II GREY HEADLAMP 5LED FLOOD RoHS:是 類別:工具 >> 閃光燈 系列:Irix™ II 標(biāo)準(zhǔn)包裝:1 系列:- 類型:筆形手電筒 燈類型:LED 燈輸出:- 特點(diǎn):可變強(qiáng)度 電池大小:AA（需要 1 個(gè)） 長(zhǎng)度:- 主體材料:- |
| IXF-10A15AF | 制造商:ILSI 制造商全稱:ILSI America LLC 功能描述:Crystal Filter 3 Lead Metal Package |
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| IXF-10A15BT | 制造商:ILSI 制造商全稱:ILSI America LLC 功能描述:Crystal Filter 3 Lead Metal Package |
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