參數(shù)資料
型號(hào): IXF1010
廠商: INTEL CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁(yè)數(shù): 42/116頁(yè)
文件大小: 1392K
代理商: IXF1010
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10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
31
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
correspond to the space occupied by the DIP-2 parity bits and are set to 1 during encoding. The
“1 1” framing pattern is not included in the parity calculation. The procedure described applies to
either parity generation on the egress path or to check parity on the ingress path.
While the parity bits mimic the “1 1” pattern, the receiving end still frames successfully by syncing
onto the last cycle in a repeated “1 1” pattern, and by making use of the configured sequence length
when searching for the framing pattern.
To permit more efficient FIFO utilization, the MaxBurst1 and MaxBurst2 credits are granted and
consumed in increments of 16-byte blocks. For any given port, these credits correspond to the most
recently received FIFO status. They are not cumulative and supersede previously granted credits
for the given port. A burst transfer shorter than 16 bytes (for example, an end-of-packet fragment)
consumes an entire 16-byte credit.
A continuous stream of repeated “1 1” framing patterns indicates a disabled status link. For
example, it may be sent to indicate that the data path deskew is not yet completed or confirmed.
When a repeated “1 1” pattern is detected, all outstanding credits are cancelled and set to zero.
Figure 9. Example of DIP-2 Encoding
DIP2 parity bits
(DIP2[1: 0])
a and b are all set to 1
during encoding
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