參數(shù)資料
型號: IXF1010
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù): 53/116頁
文件大?。?/td> 1392K
代理商: IXF1010
10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
41
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.4.9
Autoscan Operation
The Autoscan PHY Address Enable Register (Table 84, “Autoscan PHY Address Enable Register
(Addr: 0x682)” on page 110) is used to determine which PHY addresses are used for each of the
ten IXF1010 ports. The Autoscan PHY Address Enable Register is 32 bits wide, which allows for
PHY addresses 0 - 31 to be used. The bits set in this register correspond to consecutive MAC ports.
The Least Significant Bit (LSB) set in the Address Enable Register is port 0 for the IXF1010; the
next significant bit set is assumed to be port 1, and this continues on to port 9. If more than 10 bits
are set, the bits beyond the tenth bit are ignored. If less than 10 bits are set, the round-robin process
reads only the PHY registers for the reduced MAC port count.
The autoscan function stores the 32 registers in each external PHY (up to 10) internally in the
IXF1010. Autoscan is enabled by setting bit 1 of the MDI Control Register (Table 85, “MDI
Control Register (Addr: 0x683)” on page 111). When enabled, autoscan runs continuously, reading
each PHY register. When a PHY register access is instigated through the MDIO interface, the
current autoscan register Read is completed before the MDIO register access starts. Upon
completion of the MDIO access, the autoscan functionality restarts from the last autoscan register
access prior to the MDIO register access.
For example, the IXF1010 is connected to PHYs addressed 20-29, with the IXF1010 port 0
connected to PHY address 20, and Port 1 connected to PHY address 21. This is continued to port 9,
which is connected to PHY address 29. To enable autoscan for all 10 ports on the IXF1010, bits
29:20 in the Autoscan PHY Address Enable Register must be set to 1 and all other bits set to a 0.
This enables the autoscan to read PHY addresses 20-29, which allows all 32 registers of each PHY
to be stored in the connected IXF1010 ports (refer to Table 34, “PHY Autoscan Register Map” on
3.5
LED Interface
3.5.1
Introduction
The IXF1010 uses a serial interface consisting of three signals to provide LED data to some form
of external driver. This interface provides the data for 30 separate direct drive LEDs and allows
three LEDs per MAC port.
There are two modes of operation, each with its own separate LED decode mapping. Modes of
operation and LEDs are detailed in “Modes of Operation”.
3.5.2
Modes of Operation
Mode selection is accomplished by using the LED_SEL_MODE bit. This bit is globally selected
and controls the operation of all ports (see Table 68, “LED Control Register (Addr: 0x509)” on
There are two modes of operation:
Mode 0: (LED_SEL_MODE = 0 [Default]): This mode selects operations compatible with the
SGS Thompson M5450 Led Display Driver Device. This device converts the serial data stream,
output by the IXF1010, into 30 direct-drive LED outputs.
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