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參數(shù)資料
| 型號： | IXF1010 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552 |
| 文件頁數(shù)： | 48/116頁 |
| 文件大?。?/td> | 1392K |
| 代理商： | IXF1010 |
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10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
37
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.4
MDIO Control and Interface
3.4.1
MDIO Interface
IXF1010 supports the IEEE 802.3 MII Management Interface, also known as the Management
Data Input/Output (MDIO) Interface. This interface allows the IXF1010 to monitor and control
each of the PHY devices that are connected to the device’s 10 ports.
3.4.2
General Description
The MDIO Master Interface block is implemented once in the IXF1010. The MDIO Interface
block contains the logic through which the user accesses the registers in PHY devices connected to
the MDIO/MDC interface, controlled by each port.
The MDIO Master Interface block supports the management frame format, specified by IEEE
802.3, Clause 22, Section 2.4.5. This block also supports single MDI access via the CPU interface
and an autoscan mode. Autoscan allows the MDIO master to read all 32 registers of the per-port
PHYs and store the contents in the IXF1010. This ability provides an external CPU-ready access to
the PHY register contents via a single CPU Read without the latency of waiting on the low-speed
serial MDIO data bus for each register access.
3.4.3
MDIO Register Descriptions
Table 38, “MDIO Block Register Map” on page 75 provides an overview of the MDIO Register set
“MDI Control Register (Addr: 0x683)” on page 111 provide a register-by-register bit definition of
the MDIO Register set.
3.4.4
Clear When Done
The MDI Command Register bit, in the MDI Single Command and Address Register, clears upon
command completion and is set by the user to start the requested single MDIO Read or Write
operation. This bit is cleared automatically upon operation completion.
3.4.5
MDC Generation
The MDC clock is used for the MDIO/MDC interface. The frequency of the MDC clock is
selectable by setting the MDC speed bit in the MDI Control Register (see Table 85, “MDI Control
3.4.5.1
MDC High-Frequency Operation
The high-frequency MDC is 18 MHz, derived from the 125 MHz system clock by dividing the
frequency by 7.
The clock duty cycle is as follows:
MDC High duration: 3 x (1/125 MHz) = 3 X 8 ns = 24 ns
MDC Low duration: 4 x (1/125 MHz) = 4 X 8 ns = 32 ns
MDC runs continuously after reset
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