參數(shù)資料
型號: IXF1010
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù): 28/116頁
文件大?。?/td> 1392K
代理商: IXF1010
10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
19
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
3.0
Functional Descriptions
3.1
Media Access Controller (MAC)
3.1.1
General Description
The main functional block used in the IXF1010 consists of a 100/1000 Mbps Ethernet MAC. The
MAC supports the following features:
Full compliance with the Reduced Gigabit Media Independent Interface (RGMII)
100/1000 Mbps full-duplex operation
Independent enable/disable of any port
Detection of length error, and runt or overly large packets
RMON statistics and error counters
Cyclic Redundancy Check (CRC) calculation and error detection
Programmable option to:
— Filter packets with errors
— Filter, broadcast, multicast, and unicast address packets
— Automatically pad transmitted packets less than the minimum frame size
Compliance with IEEE 802.3x Standard for Flow Control (symmetric pause capability)
The MAC is fully integrated, designed for use with Ethernet 802.3 Frame types, and is compliant to
all of the required IEEE 802.3 MAC requirements.
The MAC adds preamble and SFD to all frames sent to it (transmit path) and removes preamble
and SFD on all frames received by it (receive path). A CRC check is also applied to all transmit and
receive packets. Packets with a bad CRC are marked, counted in the statistics block, and may be
optionally dropped.
The MAC operates in full-duplex mode only. The PHY, to which the MAC is attached, must
advertise full-duplex mode during any auto-negotiation process.
3.1.2
Features
The following sections cover the MAC functions.
3.1.2.1
Padding of Undersized Frames on Transmit
The padding feature allows Ethernet frames smaller than 64 bytes to be transferred across the
SPI4-2 interface and automatically padded up to 64 bytes by the MAC. This feature is enabled by
setting bit 7 of the DiverseConfigWrite Register = 1 (Address Port_Index + 0x18h).
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