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參數(shù)資料
| 型號(hào)： | IXF1010 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552 |
| 文件頁(yè)數(shù)： | 54/116頁(yè) |
| 文件大小： | 1392K |
| 代理商： | IXF1010 |
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IXF1010 — 10-Port 100/1000 Mbps Ethernet MAC
42
Preliminary Datasheet
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
Mode 1: (LED_SEL_MODE = 1): This mode is used with standard TTL (74LS595) or HCMOS
(74HC595) octal shift registers with latches, providing the most general and cost-effective
implementation of the serial data stream conversion.
In addition to these physical modes of operation, there are two types of specific LED data decodes
available. This option is a global selection and controls the operation of all ports (see Table 68,
3.5.3
LED Interface Signal Description
The IXF1010 LED Interface consists of three output signal pins that are 2.5V CMOS level pads.
Table 11 provides LED signal names, pin numbers, and descriptions.
3.5.4
Mode 0: Detailed Operation
Note:
Please refer to the SGS Thompson M5450 datasheet for device-operation information.
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each
LED is placed in turn on the serial data line and clocked out by the LED_CLK. Figure 15 on
page 42 shows the basic timing relationship and relative positioning in the data stream of each bit.
Figure 15 shows the 36 clocks that are output on the LED_CLK pin. The data changes on the
falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is
valid during the rising edge of the LED_CLK, which is used to clock the data into the M5450
device.The actual data shown in Figure 15 consists of a chain of 36 bits only, 30 of which are valid
LED DATA. The 36-bit data chain is built up as follows:
Table 11. LED Pin Descriptions
Pin Name
Pin #
Pin Description
LED_CLK
A20
LED_CLK: This signal is an output that provides a continuous clock
synchronous to the serial data stream output on the LED_DATA pin. This
clock has a maximum speed of 0.5 MHz
The behavior of this signal remains constant in all modes of operation.
LED_DATA
A19
LED_DATA: This signal provides the data, in various formats, as a serial bit
stream. The data must be valid on the rising edge of the LED_CLK signal.
In Mode 0, the data presented on this pin is TRUE (Logic 1 = High).
In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low).
LED_LATCH
K18
LED_LATCH: This is an output pin and the signal is used only in Mode 1 as
the Latch enable for the shift register chain.
This signal is not used in Mode 0, and should be left unconnected.
Figure 15. Mode 0 Timing Diagram
1
23 24 25 26 27 28 29 30
135
26
23
4
LED_CLK
LED_DATA
LED_LATCH
34
27
33
32
31
30
29
28
36
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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