參數(shù)資料
型號: IXF1010
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù): 59/116頁
文件大?。?/td> 1392K
代理商: IXF1010
10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
47
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
Figure 17 provides the timing of the asynchronous interface for Read access.
3.6.2.2
Write Access
The Write process involves the following:
Detect assertion of Asynchronous Write control signal and latch address
Detect de-assertion of Asynchronous Write control signal and latch data
Generate internal Write strobe
Assert Asynchronous Ready signal for required length of time
Figure 18 shows the timing of the asynchronous interface for Write access.
Figure 17. Read Timing Diagram - Asynchronous Interface
Tcah
uPx_Add[10:0]
uPx_Cs
uPx_Rd
Tcrh
Tcas
Tcrr
Tcdrh
Tcdrs
uPx_Data[31:0]
uPx_Rdy
Tcdrh
Figure 18. Write Timing Diagram - Asynchronous Interface
Tcah
uPx_Add[10:0]
uPx_Cs
uPx_Wr
Tcwh
Tcas
Tcwl
Tcdwh
Tcdws
uPx_Data[31:0]
uPx_Rdy
Tcyd
Tcdwh
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