參數(shù)資料
型號： IXF1010
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 10 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, CBGA552
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552
文件頁數(shù)： 10/116頁
文件大?。?/td> 1392K
代理商： IXF1010
10-Port 100/1000 Mbps Ethernet MAC — IXF1010
Preliminary Datasheet
107
Document #: 249839
Revision #: 001
Rev. Date: April 29, 2002
Table 79. TX FIFO Overflow Event Register (Addr: 0x61E)
Bit
Name
Description
Type1
Default
Register Description: This register provides status that a FIFO- full situation has occurred (for
example, a FIFO overflow). The bit position equals the port number.
This register is cleared on Read.
0x00000000
31:10
Reserved
RO
0x000000
9
TX FIFO Overflow
Event Port 9
Port 9
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
8
TX FIFO Overflow
Event Port 8
Port 8
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
7
TX FIFO Overflow
Event Port 7
Port 7
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
6
TX FIFO Overflow
Event Port 6
Port 6
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
5
TX FIFO Overflow
Event Port 5
Port 5
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
4
TX FIFO Overflow
Event Port 4
Port 4
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
3
TX FIFO Overflow
Event Port 3
Port 3
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
2
TX FIFO Overflow
Event Port 2
Port 2
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
1
TX FIFO Overflow
Event Port 1
Port 1
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
TX FIFO Overflow
Event Port 0
Port 0
1 = FIFO overflow event occurred
0 = FIFO overflow event did not occur
RR
0
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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