參數(shù)資料
型號(hào): ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 77/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
77 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.2.2
GDMA slave mode
Bits MODE[1:0] = 00: data strobes DIOR (read) and DIOW (write); see
Figure 30
Bits MODE[1:0] = 01: data strobes DIOR (read) and DACK (write); see
Figure 31
Bits MODE[1:0] = 10: data strobes DACK (read and write); see
Figure 32
.
Table 105: GDMA slave mode timing parameters
V
CC(I/O)
= 3.3 V; V
CC(3V3)
= 3.3 V; V
GND
= 0 V; T
amb
=
40
°
C to +85
°
C.
Symbol
Parameter
T
cy1
read/write cycle time
t
su1
DREQ set-up time before first DACK on
t
d1
DREQ on delay after last strobe off
t
h1
DREQ hold time after last strobe on
t
w1
DIOR/DIOW pulse width
t
w2
DIOR/DIOW recovery time
t
d2
read data valid delay after strobe on
t
h2
read data hold time after strobe off
t
h3
write data hold time after strobe off
t
su2
write data set-up time before strobe off
t
su3
DACK setup time before DIOR/DIOW assertion
t
a1
DACK deassertion after DIOR/DIOW deassertion
Min
75
10
33.33
0
39
36
-
-
1
10
0
0
Max
-
-
-
53
600
-
20
5
-
-
-
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 30. GDMA slave mode timing: DIOR (master) and DIOW (slave).
th1
tw1
tsu1
td1
tsu2
td2
th2
Tcy1
(write) DATA[15:0]
(read) DATA[15:0]
DREQ
(2)
DACK
(1)
DIOR/DIOW
(1)
MGT500
tsu3
tw2
ta1
th3
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