參數(shù)資料
型號(hào): ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁(yè)數(shù): 13/87頁(yè)
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
13 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40
×
PLL clock
multiplier generates the internal sampling clock of 480 MHz.
8.1 DMA interface, DMA handler and DMA registers
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA command register to start a DMA transfer (see
Table 49
). The command opcode determines whether a generic DMA, Parallel I/O
(PIO) or Multiword DMA (MDMA) transfer will start. The handler interfaces to the
same FIFO (internal RAM) as used by the USB core. On receiving the DMA
command, the DMA handler directs the data from the endpoint FIFO to the external
DMA device or from the external DMA device to the endpoint FIFO.
The DMA interface configures the timing and the DMA handshake. Data can be
transferred using either the DIOR and DIOW strobes or by the DACK and DREQ
handshakes. The DMA configurations are set up by writing to the DMA Configuration
register (see
Table 54
and
Table 55
).
For an IDE-based storage interface, applicable DMA modes are PIO and MDMA
(Multiword DMA; ATA).
For a generic DMA interface, DMA modes that can be used are Generic DMA
(GDMA) slave.
Remark:
The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see
Section 9.4
.
8.2 Hi-Speed USB transceiver
The analog transceiver directly interfaces to the USB cable through integrated
termination resistors. The high-speed transceiver requires an external resistor
(12.0 k
±
1 %) between pin RREF and ground to ensure an accurate current mirror
that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated
as well. This makes the ISP1583 compliant to Hi-Speed USB and Original USB,
supporting both the high-speed and full-speed physical layers. After automatic speed
detection, the Philips Serial Interface Engine (SIE) sets the transceiver to use either
high-speed or full-speed signaling.
8.3 MMU and integrated RAM
The Memory Management Unit (MMU) and the integrated RAM provide the
conversion between the USB speed (full-speed: 12 Mbit/s; high-speed: 480 Mbit/s)
and the microcontroller handler or the DMA handler. The data from the USB bus is
stored in the integrated RAM, which is cleared only when the microcontroller has read
or written all data from or to the corresponding endpoint buffer or when the DMA
handler has read or written all data from or to the endpoint buffer. The OUT endpoint
buffer can also be cleared forcibly by setting bit CLBUF in the Control Function
register. A total of 8 kbytes RAM is available for buffering.
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ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
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