參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 15/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
15 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.6.3
HS detection
The ISP1583 handles more than one electrical state—full-speed (FS) or high-speed
(HS)—under the USB specification. When the USB cable is connected from the
peripheral to the host controller, the ISP1583 defaults to the FS state until it sees a
bus reset from the host controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. Chirping must be done with the
pull-up resistor connected and the internal termination resistors disabled. If the HS
handshake shows that there is an HS host connected, then the ISP1583 switches to
the HS state.
In the HS state, the ISP1583 should observe the bus for periodic activity. If the bus
remains inactive for 3 ms, the peripheral switches to the FS state to check for a
Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected
for the designated time (100
μ
s to 875
μ
s; refer to section 7.1.7.6 of the USB
specification Rev. 2.0), the ISP1583 switches to the HS chirp state to perform an HS
detection handshake. Otherwise, the ISP1583 remains in the FS state adhering to the
bus-suspend specification.
8.7 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel or serial conversion, bit-stuffing or
destuffing, CRC checking or generation, Packet IDentifier (PID) verification or
generation, address recognition, handshake evaluation or generation.
8.8 SoftConnect
The connection to the USB is established by pulling pin DP (for full-speed devices)
HIGH through a 1.5 k
pull-up resistor. In the ISP1583, an external 1.5 k
pull-up
resistor must be connected between pin RPU and 3.3 V. The RPU pin connects the
pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see
Table 21
and
Table 22
). After a hardware reset, the pull-up resistor is disconnected by default
(bit SOFTCT = 0). The USB bus reset does not change the value of bit SOFTCT.
When the V
BUS
is not present, the SOFTCT bit must be set to logic 0 to comply with
the back-drive voltage.
8.9 System controller
The system controller implements the USB power-down capabilities of the ISP1583.
Registers are protected against data corruption during wake-up following a resume
(from the suspend state) by locking the write access until an unlock code has been
written in the Unlock Device register (see
Table 89
and
Table 90
).
8.10 Modes of operation
The ISP1583 has two bus configuration modes, selected via pin BUS_CONF at
power-up:
相關(guān)PDF資料
PDF描述
ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
ISP1760BE Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications
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ISP1761BE Hi-Speed Universal Serial Bus On-The-Go controller
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