參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 36/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
36 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3 Data flow registers
9.3.1
Endpoint Index register (address: 2Ch)
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
Table 31
.
The following registers are indexed:
Buffer Length
Buffer Status
Control Function
Data Port
Endpoint MaxPacketSize
Endpoint Type.
For example, to access the OUT data buffer of endpoint 1 using the Data Port
register, the Endpoint Index register has to be written first with 02h.
Remark:
The Endpoint Index register and the DMA Endpoint Index register must not
point to the same endpoint.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
IEP5RX
IEP4TX
IEP4RX
IEP3TX
IEP3RX
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
-
IEP0SETUP Logic 1 enables interrupt for the setup data received on endpoint 0.
IEVBUS
Logic 1 enables interrupt for V
BUS
sensing.
IEDMA
Logic 1 enables interrupt on DMA status change detection.
IEHS_STA
Logic 1 enables interrupt on detection of a high-speed status
change.
IERESM
Logic 1 enables interrupt on detection of a resume state.
IESUSP
Logic 1 enables interrupt on detection of a suspend state.
IEPSOF
Logic 1 enables interrupt on detection of a Pseudo SOF.
IESOF
Logic 1 enables interrupt on detection of an SOF.
IEBRST
Logic 1 enables interrupt on detection of a bus reset.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the control IN endpoint 0.
Logic 1 enables interrupt from the control OUT endpoint 0.
reserved
4
3
2
1
0
Table 30:
Bit
Interrupt Enable register: bit description
…continued
Symbol
Description
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