參數(shù)資料
型號(hào)： ISP1583
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus peripheral controller
中文描述： 高速通用串行總線外設(shè)控制器
文件頁(yè)數(shù)： 34/87頁(yè)
文件大?。?/td> 420K
代理商： ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
34 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
No interrupt is designed for OTG. The V
BUS
interrupt, however, may assert as a side effect during the
V
BUS
pulsing (see note 2).
When OTG is in progress, the V
BUS
interrupt may be set because V
BUS
is charged over V
BUS
sensing
threshold or the OTG host has turned on the V
BUS
supply to the device. Even if the V
BUS
interrupt is
found during SRP, the device should complete data-line pulsing and V
BUS
pulsing before starting the
B_session_valid detection.
OTG implementation applies to the device with self-power capability. If the device works in sharing
mode, it should provide a switch circuit to supply power to the ISP1583 core during SRP.
Session Request Protocol (SRP):
The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing
followed by V
BUS
pulsing. The A-device can detect either data-line pulsing or V
BUS
pulsing.
The ISP1583 can initiate the B-device SRP by performing the following steps:
1. Detect initial conditions: read bit INITCOND of the OTG register.
2. Start data-line pulsing: set bit DP of the OTG register to logic 1.
3. Wait for 5 ms to 10 ms.
4. Stop data-line pulsing: set bit DP of the OTG register to logic 0.
5. Start V
BUS
pulsing: set bit VP of the OTG register to logic 1.
6. Wait for 10 ms to 20 ms.
7. Stop V
BUS
pulsing: set bit VP of the OTG register to logic 0.
8. Discharge V
BUS
for about 30 ms: optional by using bit DISCV of the OTG register.
9. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG
disabled.
The B-device must complete both data-line pulsing and V
BUS
pulsing within 100 ms.
Remark:
When disabling, OTG data-line pulsing bit DP and V
BUS
pulsing bit VP must
be cleared by writing logic 1.
9.2.5
Interrupt Enable register (address: 14h)
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated bits IEPnRX or IEPnTX,
here n represents the endpoint number. All interrupts can be globally disabled
through bit GLINTENA in the Mode register (see
Table 21
).
2
DISCV
Set to logic 1 to discharge V
BUS
. The device discharges V
BUS
before
starting a new SRP. The discharge can take as long as 30 ms for
V
BUS
to be charged less than 0.8 V. This bit must be cleared (write
logic 0) before starting a session end detection.
Set to logic 1 to start V
BUS
pulsing. This bit must be set for more than
16 ms and must be cleared before 26 ms.
1 —
Enables the OTG function. The V
BUS
sensing functionality will
be bypassed.
1
VP
0
OTG
0 —
Normal operation. All OTG control bits will be masked. Status
bits are undefined.
Table 28:
Bit
OTG register: bit description
[1]
…continued
Symbol
Description
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