參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 31/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
31 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
When SoftConnect and V
BUS
are not present (except in OTG), the USB bus activities
are not qualified. Therefore, the chip will follow the suspend command to enter
suspend mode (the clock is controlled by bit CLKAON).
When V
BUS
is off, the 1.5 k
pull-up resister is disconnected from pin DP in
approximately 4 ns via bit SOFTCT in the Mode register and a suspend interrupt is
set with some latency (debounce and disqualify USB traffic).
When bit SOFTCT is set to logic 0, no interrupt is generated. The firmware can issue
a suspend command, followed by the resetting of bit SOFTCT to suspend the chip.
If OTG is logic 1, the pull-up resistor on pin DP depends on D+ line (V
BUS
sensing
status). Bit DP operates as normal, so the firmware must mask suspend and wake-up
interrupt events. When SRP is completed, the device should clear OTG.
If OTG is logic 0, the status of the pull-up resistor on DP is referred to in
Table 23
.
3
GLINTENA
Global Interrupt Enable:
Logic 1 enables all interrupts. Individual
interrupts can be masked by clearing the corresponding bits in the
Interrupt Enable register.
When this bit is not set, an unmasked interrupt will not generate
an interrupt trigger on the interrupt pin. If global interrupt, however,
is enabled while there is any pending unmasked interrupt, an
interrupt signal will be immediately generated on the interrupt pin.
(If the interrupt is set to pulse mode, the interrupt events that were
generated before the global interrupt is enabled may be dropped.)
Wake-up on Chip selection:
Logic 1 enables wake-up from
suspend mode through a valid register read on the ISP1583. (A
read will invoke the chip clock to restart. If you write to the register
before the clock gets stable, it may cause malfunctioning.)
The SUSPEND pin output control.
2
WKUPCS
1
PWRON
0 —
The SUSPEND pin is HIGH when the ISP1583 is in the
suspend state. Otherwise, the SUSPEND pin is LOW.
1 —
When the device is woken up from the suspend state, there
will be a 1 ms active HIGH pulse on the SUSPEND pin. The
SUSPEND pin will remain LOW in all other states.
SoftConnect:
Logic 1 enables the connection of the 1.5 k
pull-up resistor on pin RPU to the DP line. Bus reset
value: unchanged.
0
SOFTCT
Table 23:
V
BUS
On
Status of the chip
SoftConnect = on
pull-up resistor on DP
SoftConnect = off
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
Off
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
Table 22:
Bit
Mode register: bit description
…continued
Symbol
Description
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