參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 50/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
50 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.5
Task File registers (addresses: 40h to 4Fh)
These registers allow direct access to the internal registers of an ATAPI peripheral
using PIO mode. The supported Task File registers and their functions are shown in
Table 58
. The correct peripheral register is automatically addressed via pins CS1_N,
CS0_N, DA2, DA1 and DA0 (see
Table 59
).
Table 57:
Bit
7 to 6
DMA Hardware register: bit description
Symbol
Description
ENDIAN[1:0]
These bits determine whether the data bus is swapped between
the internal RAM and the DMA bus. This only applies for modes
GDMA (slave) and MDMA (master).
00 —
normal data representation; 16-bit bus: MSB on
DATA[15:8] and LSB on DATA[7:0].
01 —
swapped data representation; 16-bit bus: MSB on
DATA[7:0] and LSB on DATA[15:8].
10 —
reserved.
11 —
reserved.
Remark:
While operating with the 8-bit data bus, bits
ENDIAN[1:0] should be always set to logic 00.
Selects the polarity of the End-Of-Transfer input; used in GDMA
slave mode only.
5
EOT_POL
0 —
EOT is active LOW
1 —
EOT is active HIGH.
Selects DMA master/slave mode.
4
MASTER
0 —
GDMA slave mode
1 —
MDMA master mode.
Selects the DMA acknowledgment polarity.
3
ACK_POL
0 —
DACK is active LOW
1 —
DACK is active HIGH.
Selects the DMA request polarity.
2
DREQ_POL
0 —
DREQ is active LOW
1 —
DREQ is active HIGH.
Selects the DIOW strobe polarity.
1
WRITE_POL
0 —
DIOW is active LOW
1 —
DIOW is active HIGH.
Selects the DIOR strobe polarity.
0
READ_POL
0 —
DIOR is active LOW
1 —
DIOR is active HIGH.
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