參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 54/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
54 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 70:
Bit
Symbol
DMA Interrupt Reason register: bit allocation
15
14
TEST3
13
12
11
10
9
8
reserved
GDMA_
STOP
0
0
R/W
4
READ_1F0
EXT_EOT
INT_EOT
INTRQ_
PENDING
0
0
R/W
1
CMD_
INTRQ_OK
0
0
R/W
DMA_
XFER_OK
0
0
R/W
0
reserved
Reset
Bus reset
Access
Bit
Symbol
-
-
-
-
-
-
0
0
0
0
R
7
R
6
R
5
R/W
3
BSY_
DONE
0
0
R/W
R/W
2
TF_RD_
DONE
0
0
R/W
reserved
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
-
-
R/W
R/W
R/W
R/W
R/W
Table 71:
Bit
15
DMA Interrupt Reason register: bit description
Symbol
Description
TEST3
This bit is set when a DMA transfer for a packet (OUT transfer)
terminates before the whole packet has been transferred. This
bit is a status bit, and the corresponding mask bit of this
register is always 0. Writing any value other than 0 has no
effect.
14 to 13 -
reserved
12
GDMA_STOP
When the GDMA_STOP command is issued to the DMA
Command registers, it means the DMA transfer has
successfully terminated.
11
EXT_EOT
Logic 1 indicates that an external EOT is detected. This is
applicable only in GDMA slave mode.
10
INT_EOT
Logic 1 indicates that an internal EOT is detected; see
Table 72
.
9
INTRQ_
PENDING
INTRQ.
8
DMA_XFER_OK
Logic 1 indicates that the DMA transfer has been completed
(DMA Transfer Counter has become zero). This bit is only used
in GDMA (slave) mode and MDMA (master) mode.
7 to 5
-
reserved
4
READ_1F0
Logic 1 indicates that the 1F0 FIFO contains unread data and
the microcontroller can start reading data.
3
BSY_DONE
Logic 1 indicates that the BSY status bit has become zero and
polling has been stopped.
2
TF_RD_DONE
Logic 1 indicates that the Read Task Files command has been
completed.
1
CMD_INTRQ_OK Logic 1 indicates that all bytes from the FIFO have been
transferred (DMA Transfer Count zero) and an interrupt on pin
INTRQ was detected.
0
-
reserved
Logic 1 indicates that a pending interrupt was detected on pin
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