參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 76/87頁
文件大小: 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
76 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except
for the Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04h and 05h also use a 16-bit data bus.
(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the
current cycle after t
su4
following the assertion of DIOR or DIOW. The following three cases are distinguished:
a) Device keeps IORDY released (high-impedance): no wait state is generated.
b) Device negates IORDY during t
su4
, but re-asserts IORDY before t
su4
expires: no wait state is generated.
c) Device negates IORDY during t
su4
and keeps IORDY negated for at least 5 ns after t
su4
expires: a wait state is generated.
The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read data on lines
DATAn must be valid at t
d1
before IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 29. PIO mode timing.
HIGH
(write) DATA[7:0]
(2)
(read) DATA[7:0]
(2)
device
(1)
address
valid
DIOR, DIOW
(4)
IORDY
(3a)
IORDY
(3b)
IORDY
(3c)
tw1
tw2
th1
tsu1
tsu2
tsu5
tsu4
tsu4
tw3
th2
tsu3
td2
th3
(min)
Tcy1
MGT499
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