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| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 95/102頁 |
| 文件大小： | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
9.2 INSTRUCTION ENCODING
9.2.1 Overview
All instruction encodings are subsets of the general
instruction format shown in Figure 8-1. Instructions
consist of one or two primary opcode bytes, possibly
an address specifier consisting of the ‘‘mod r/m’’
byte and ‘‘scaled index’’ byte, a displacement if re-
quired, and an immediate data field if required.
Within the primary opcode or opcodes, smaller en-
coding fields may be defined. These fields vary ac-
cording to the class of operation. The fields define
such information as direction of the operation, size
of the displacements, register encoding, or sign ex-
tension.
Almost all instructions referring to an operand in
memory have an addressing mode byte following
the primary opcode byte(s). This byte, the mod r/m
byte, specifies the address mode to be used. Certain
encodings of the mod r/m byte indicate a second
addressing byte, the scale-index-base byte, follows
the mod r/m byte to fully specify the addressing
mode.
Addressing modes can include a displacement im-
mediately following the mod r/m byte, or scaled in-
dex byte. If a displacement is present, the possible
sizes are 8, 16 or 32 bits.
If the instruction specifies an immediate operand,
the immediate operand follows any displacement
bytes. The immediate operand, if specified, is always
the last field of the instruction.
Figure 9-1 illustrates several of the fields that can
appear in an instruction, such as the mod field and
the r/m field, but the Figure does not show all fields.
Several smaller fields also appear in certain instruc-
tions, sometimes within the opcode bytes them-
selves. Table 9-2 is a complete list of all fields ap-
pearing in the instruction set. Further ahead, follow-
ing Table 9-2, are detailed tables for each field.
T T T T T T T T T T T T T T T T mod T T T r/m
X
opcode
(one or two bytes)
(T represents an
opcode bit.)
ss index base d32
l
16
l
8
l
none data32
l
16
l
8
l
none
7 6 5 3 2 0
YX
‘‘s-i-b’’
address
byte
displacement
(4, 2, 1 bytes
register and address
or none)
mode specifier
7
0 7
0
YX
7 6 5 3 2 0
‘‘mod r/m’’
byte
X
YX
Y X
Y
immediate
data
(4, 2, 1 bytes
or none)
Y
Figure 9-1. General Instruction Format
Table 9-2. Fields within Instructions
Field Name
Description
Number of Bits
w
d
s
reg
mod r/m
Specifies if Data is Byte or Full Size (Full Size is either 16 or 32 Bits
Specifies Direction of Data Operation
Specifies if an Immediate Data Field Must be Sign-Extended
General Register Specifier
Address Mode Specifier (Effective Address can be a General Register)
1
1
1
3
2 for mod;
3 for r/m
2
3
3
2
3
ss
index
base
sreg2
sreg3
tttn
Scale Factor for Scaled Index Address Mode
General Register to be used as Index Register
General Register to be used as Base Register
Segment Register Specifier for CS, SS, DS, ES
Segment Register Specifier for CS, SS, DS, ES, FS, GS
For Conditional Instructions, Specifies a Condition Asserted
or a Condition Negated
4
Note:
Table 9-1 shows encoding of individual instructions.
95
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相關代理商/技術(shù)參數(shù) |
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| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
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