參數(shù)資料
型號(hào)： intel386 SX
廠(chǎng)商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線(xiàn)和24位內(nèi)部地址總線(xiàn)32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線(xiàn)和24位外部地址總線(xiàn)CPU（帶16位內(nèi)部數(shù)據(jù)總線(xiàn)和24位內(nèi)部地址總線(xiàn)32位微處理器）
文件頁(yè)數(shù)： 48/102頁(yè)
文件大?。?/td> 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
Every bus cycle continues until it is acknowledged
by the external system hardware, using the Intel386
SX Microprocessor READY
Y
input. Acknowledging
the bus cycle at the end of the first T2 results in the
shortest bus cycle, requiring only T1 and T2. If
READY
Y
is not immediately asserted however, T2
states are repeated indefinitely until the READY
Y
input is sampled active.
The address pipelining option provides a choice of
bus cycle timings. Pipelined or non-pipelined ad-
dress timing is selectable on a cycle-by-cycle basis
with the Next Address (NA
Y
) input.
When address pipelining is selected the address
(BHE
Y
, BLE
Y
and A
23
–A
1
) and definition (W/R
Y
,
D/C
Y
, M/IO
Y
and LOCK
Y
) of the next cycle are
available before the end of the current cycle. To sig-
nal their availability, the Intel386 SX Microprocessor
address status output (ADS
Y
) is asserted. Figure
5.5 illustrates the fastest read cycles with pipelined
address timing.
Note from Figure 5.5 the fastest bus cycles using
pipelined address require only two bus states,
named
T1P
and
T2P
. Therefore cycles with pipe-
lined address timing allow the same data bandwidth
as non-pipelined cycles, but address-to-data access
time is increased by one T-state time compared to
that of a non-pipelined cycle.
READ AND WRITE CYCLES
Data transfers occur as a result of bus cycles, classi-
fied as read or write cycles. During read cycles, data
is transferred from an external device to the proces-
sor. During write cycles, data is transferred from the
processor to an external device.
240187–21
Idle states are shown here for diagram variety only. Write cycles are
not
always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 5.6. Various Bus Cycles with Non-Pipelined Address (zero wait states)
48
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