參數(shù)資料
型號(hào)： intel386 SX
廠商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器）
文件頁數(shù)： 61/102頁
文件大?。?/td> 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
RESET should remain asserted for at least 15 CLK2
periods to ensure it is recognized throughout the
Intel386 SX Microprocessor, and at least 80 CLK2
periods if self-test is going to be requested at the
falling edge. RESET asserted pulses less than 15
CLK2 periods may not be recognized. RESET puls-
es less than 80 CLK2 periods followed by a self-test
may cause the self-test to report a failure when no
true failure exists.
Provided the RESET falling edge meets setup and
hold times t
25
and t
26
, the internal processor clock
phase is defined at that time as illustrated by Figure
5.19 and Figure 7.7.
A self-test may be requested at the time RESET
goes inactive by having the BUSY
Y
input at a LOW
level as shown in Figure 5.19. The self-test requires
approximately (2
20
a
60) CLK2 periods to com-
plete. The self-test duration is not affected by the
test results. Even if the self-test indicates a problem,
the Intel386 SX Microprocessor attempts to proceed
with the reset sequence afterwards.
After the RESET falling edge (and after the self-test
if it was requested) the Intel386 SX Microprocessor
performs an internal initialization sequence for ap-
proximately 350 to 450 CLK2 periods.
240187–33
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t23 and t24) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
Figure 5.18. Requesting Hold from Idle Bus (NA
Y
active)
61
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相關(guān)代理商/技術(shù)參數(shù)
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