參數(shù)資料
型號(hào)： intel386 SX
廠商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器）
文件頁(yè)數(shù)： 34/102頁(yè)
文件大小： 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
31
12
11
10
9
8
7
6
5
4
3
2
1
0
System
Software
Defineable
U
D
S
R
D
W
PAGE FRAME ADDRESS 31..12
0
0
D
A
0
0
P
Figure 4.12. Page Table Entry (Points to Page)
Page Fault Register
CR2 is the Page Fault Linear Address register. It
holds the 32-bit linear address which caused the last
Page Fault detected.
Page Descriptor Base Register
CR3 is the Page Directory Physical Base Address
Register. It contains the physical starting address of
the Page Directory (this value is truncated to a 24-bit
value associated with the Intel386 SX CPU’s 16
megabyte physical memory limitation). The lower 12
bits of CR3 are always zero to ensure that the Page
Directory is always page aligned. Loading it with a
MOV CR3, reg
instruction causes the page table en-
try cache to be flushed, as will a task switch through
a TSS which changes the value of CR0.
Page Directory
The Page Directory is 4k bytes long and allows up to
1024 page directory entries. Each page directory en-
try contains information about the page table and
the address of the next level of tables, the Page
Tables. The contents of a Page Directory Entry are
shown in figure 4.11. The upper 10 bits of the linear
address (A
31
–A
22
) are used as an index to select
the correct Page Directory Entry.
The page table address contains the upper 20 bits
of a 32-bit physical address that is used as the base
address for the next set of tables, the page tables.
The lower 12 bits of the page table address are zero
so that the page table addresses appear on 4 kbyte
boundaries. For a Intel386 DX CPU system the up-
per 20 bits will select one of 2
20
page tables, but for
a Intel386 SX Microprocessor system the upper 20
bits only select one of 2
12
page tables. Again, this is
because the Intel386 SX Microprocessor is limited to
a 24-bit physical address and the upper 8 bits (A
24
–
A
31
) are truncated when the address is output on its
24 address pins.
Page Tables
Each Page Table is 4K bytes long and allows up to
1024 Page table Entries. Each page table entry con-
tains information about the Page Frame and its ad-
dress. The contents of a Page Table Entry are
shown in figure 4.12. The middle 10 bits of the linear
address (A
21
–A
12
) are used as an index to select
the correct Page Table Entry.
The Page Frame Address contains the upper 20 bits
of a 32-bit physical address that is used as the base
address for the Page Frame. The lower 12 bits of the
Page Frame Address are zero so that the Page
Frame addresses appear on 4 kbyte boundaries. For
an Intel386 DX CPU system the upper 20 bits will
select one of 2
20
Page Frames, but for an
Intel386 SX Microprocessor system the upper 20
bits only select one of 2
12
Page Frames. Again, this
is because the Intel386 SX Microprocessor is limited
to a 24-bit physical address space and the upper 8
bits (A
24
–A
31
) are truncated when the address is
output on its 24 address pins.
Page Directory/Table Entries
The lower 12 bits of the Page Table Entries and
Page Directory Entries contain statistical information
about pages and page tables respectively. The P
(Present) bit indicates if a Page Directory or Page
Table entry can be used in address translation. If
P
e
1, the entry can be used for address translation.
If P
e
0, the entry cannot be used for translation. All
of the other bits are available for use by the soft-
ware. For example, the remaining 31 bits could be
used to indicate where on disk the page is stored.
The A (Accessed) bit is set by the Intel386 SX CPU
for both types of entries before a read or write ac-
cess occurs to an address covered by the entry. The
D (Dirty) bit is set to 1 before a write to an address
covered by that page table entry occurs. The D bit is
undefined for Page Directory Entries. When the P, A
and D bits are updated by the Intel386 SX CPU, the
processor generates a Read- Modify-Write cycle
which locks the bus and prevents conflicts with oth-
er processors or peripherals. Software which modi-
fies these bits should use the LOCK prefix to ensure
the integrity of the page tables in multi-master sys-
tems.
The 3 bits marked system software definable in Fig-
ures 4.11 and Figure 4.12 are software definable.
System software writers are free to use these bits
for whatever purpose they wish.
34
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