參數(shù)資料
型號(hào)： intel386 SX
廠(chǎng)商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線(xiàn)和24位內(nèi)部地址總線(xiàn)32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線(xiàn)和24位外部地址總線(xiàn)CPU（帶16位內(nèi)部數(shù)據(jù)總線(xiàn)和24位內(nèi)部地址總線(xiàn)32位微處理器）
文件頁(yè)數(shù)： 27/102頁(yè)
文件大?。?/td> 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
(Present) Bit is 1 if the segment is loaded in physical
memory. If P
e
0 then any attempt to access this
segment causes a not present exception (exception
11). The Descriptor Privilege Level, DPL, is a two bit
field which specifies the protection level, 0–3, asso-
ciated with a segment.
The Intel386 SX Microprocessor has two main cate-
gories of segments: system segments and non-sys-
tem segments (for code and data). The segment bit,
S, determines if a given segment is a system seg-
ment or a code or data segment. If the S bit is 1 then
the segment is either a code or data segment; if it is
0 then the segment is a system segment.
Code and Data Descriptors (S
e
1)
Figure 4.5 shows the general format of a code and
data descriptor and Table 4.1 illustrates how the bits
in the Access Right Byte are interpreted.
31
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
LIMIT
19 . . . 16
ACCESS
RIGHTS
BYTE
BASE
BASE 31 . . . 24
G
D
0
AVL
23 . . . 16
a
4
D/B
1
e
Default Instructions Attributes are 32-Bits
0
e
Default Instruction Attributes are 16-Bits
Available field for user or OS
AVL
G
Granularity Bit
1
e
Segment length is page granular
0
e
Segment length is byte granular
Bit must be zero (0) for compatibility with future processors
0
Figure 4.5. Code and Data Descriptors
Table 4.1. Access Rights Byte Definition for Code and Data Descriptors
Bit
Name
Function
Position
7
Present (P)
P
e
1
P
e
0
Segment is mapped into physical memory.
No mapping to physical memory exists, base and limt are
not used.
Segment privilege attribute used in privilege tests.
6–5
Descriptor Privilege
Level (DPL)
Segment Descrip-
tor (S)
4
S
e
1
S
e
0
Code or Data (includes stacks) segment descriptor
System Segment Descriptor or Gate Descriptor
3
2
Executable (E)
Expansion Direc-
tion (ED)
Writeable (W)
E
e
0
ED
e
0 Expand up segment, offsets must be
s
limit.
ED
e
1 Expand down segment, offsets must be
l
limit.
W
e
0 Data segment may not be written into.
W
e
1 Data segment may be written into.
Descriptor type is data segment:
If
Data
Segment
(S
e
1,
1
*
E
e
0)
3
2
Executable (E)
Conforming (C)
E
e
1
C
e
1
Descriptor type is code segment:
Code segment may only be executed
when CPL
t
DPL and CPL
remains unchanged.
Code segment may not be read.
Code segment may be read.
If
Code
Segment
(S
e
1,
E
e
1)
1
Readable (R)
R
e
0
R
e
1
*
0
Accessed (A)
A
e
0
A
e
1
Segment has not been accessed.
Segment selector has been loaded into segment register
or used by selector test instructions.
27
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