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| 型號(hào)： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 30/102頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
Table 4.2. Descriptor Types Used for Control Transfer
Control Transfer Types
Operation Types
Descriptor
Referenced
Descriptor
Table
Intersegment within the same privilege level
JMP, CALL RET, IRET
*
Code Segment
GDT/LDT
Intersegment to the same or higher privilege level
Interrupt within task may change CPL
CALL
Call Gate
GDT/LDT
Interrupt instruction
Exception External
Interrupt
Trap or
Interrupt
Gate
IDT
Intersegment to a lower privilege level
(changes task CPL)
RET, IRET
*
Code Segment
GDT/LDT
CALL, JMP
Task State
Segment
GDT
Task Switch
CALL, JMP
Task Gate
GDT/LDT
IRET
**
Interrupt instruction,
Exception, External
Interrupt
Task Gate
IDT
*
NT (Nested Task bit of flag register)
e
0
**
NT (Nested Task bit of flag register)
e
1
I/O Privilege
The I/O privilege level (IOPL) lets the operating sys-
tem code executing at CPL
e
0 define the least privi-
leged level at which I/O instructions can be used. An
exception 13 (General Protection Violation) is gener-
ated if an I/O instruction is attempted when the CPL
of the task is less privileged then the IOPL. The
IOPL is stored in bits 13 and 14 of the EFLAGS reg-
ister. The following instructions cause an exception
13 if the CPL is greater than IOPL: IN, INS, OUT,
OUTS, STI, CLI, LOCK prefix.
Descriptor Access
There are basically two types of segment accesses:
those involving code segments such as control
transfers, and those involving data accesses. Deter-
mining the ability of a task to access a segment in-
volves the type of segment to be accessed, the in-
struction used, the type of descriptor used and CPL,
RPL, and DPL as described above.
Any time an instruction loads a data segment regis-
ter (DS, ES, FS, GS) the Intel386 SX Microprocessor
makes protection validation checks. Selectors load-
ed in the DS, ES, FS, GS registers must refer only to
data segment or readable code segments.
Finally the privilege validation checks are performed.
The CPL is compared to the EPL and if the EPL is
more privileged than the CPL, an exception 13 (gen-
eral protection fault) is generated.
The rules regarding the stack segment are slightly
different than those involving data segments. In-
structions that load selectors into SS must refer to
data segment descriptors for writeable data seg-
ments. The DPL and RPL must equal the CPL of all
other descriptor types or a privilege level violation
will cause an exception 13. A stack not present fault
causes an exception 12.
PRIVILEGE LEVEL TRANSFERS
Inter-segment control transfers occur when a selec-
tor is loaded in the CS register. For a typical system
most of these transfers are simply the result of a call
or a jump to another routine. There are five types of
control transfers which are summarized in Table 4.2.
Many of these transfers result in a privilege level
transfer. Changing privilege levels is done only by
control transfers, using gates, task switches, and in-
terrupt or trap gates.
Control transfers can only occur if the operation
which loaded the selector references the correct de-
scriptor type. Any violation of these descriptor usage
rules will cause an exception 13.
30
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