參數(shù)資料
型號(hào)： intel386 SX
廠商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器）
文件頁(yè)數(shù)： 56/102頁(yè)
文件大小： 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
INTERRUPT ACKNOWLEDGE (INTA) CYCLES
In response to an interrupt request on the INTR in-
put when interrupts are enabled, the Intel386 SX Mi-
croprocessor performs two interrupt acknowledge
cycles. These bus cycles are similar to read cycles
in that bus definition signals define the type of bus
activity taking place, and each cycle continues until
acknowledged by READY
Y
sampled active.
The state of A
2
distinguishes the first and second
interrupt acknowledge cycles. The byte address
driven during the first interrupt acknowledge cycle is
4 (A
23
–A
3
, A
1
, BLE
Y
LOW, A
2
and BHE
Y
HIGH).
The byte address driven during the second interrupt
acknowledge cycle is 0 (A
23
–A
1
, BLE
Y
LOW, and
BHE
Y
HIGH).
The LOCK
Y
output is asserted from the beginning
of the first interrupt acknowledge cycle until the end
of the second interrupt acknowledge cycle. Four idle
bus states, T
i
, are inserted by the Intel386 SX Micro-
processor between the two interrupt acknowledge
cycles for compatibility with spec TRHRL of the
8259A Interrupt Controller.
During both interrupt acknowledge cycles, D
15
–D
0
float. No data is read at the end of the first interrupt
acknowledge cycle. At the end of the second inter-
rupt acknowledge cycle, the Intel386 SX Microproc-
essor will read an external interrupt vector from D
7
–
D
0
of the data bus. The vector indicates the specific
interrupt number (from 0–255) requiring service.
240187–28
Interrupt Vector (0–255) is read on D0–D7 at end of second interrupt Acknowledge bus cycle.
Because each Interrupt Acknowledge bus cycle is followed by idle bus states. asserting NA
Y
has no practical effect.
Choose the approach which is simplest for your system hardware design.
Figure 5.13. Interrupt Acknowledge Cycles
56
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