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參數(shù)資料
| 型號(hào)： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 51/102頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
Bus cycles always begin with T1. T1 always leads to
T2. If a bus cycle is not acknowledged during T2 and
NA
Y
is inactive, T2 is repeated. When a cycle is
acknowledged during T2, the following state will be
T1 of the next bus cycle if a bus request is pending
internally, or T
i
if there is no bus request pending, or
T
h
if the HOLD input is being asserted.
Use of pipelined address allows the Intel386 SX Mi-
croprocessor to enter three additional bus states not
shown in Figure 5.8. Figure 5.12 is the complete bus
state diagram, including pipelined address cycles.
Pipelined Address
Address pipelining is the option of requesting the
address and the bus cycle definition of the next in-
ternally pending bus cycle before the current bus
cycle is acknowledged with READY
Y
asserted.
ADS
Y
is asserted by the Intel386 SX Microproces-
sor when the next address is issued. The address
pipelining option is controlled on a cycle-by-cycle
basis with the NA
Y
input signal.
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state, the NA
Y
input is sampled at the end of every
phase one until the bus cycle is acknowledged. Dur-
ing non-pipelined bus cycles NA
Y
is sampled at the
end of phase one in every T2. An example is Cycle 2
in Figure 5.9, during which NA
Y
is sampled at the
end of phase one of every T2 (it was asserted once
during the first T2 and has no further effect during
that bus cycle).
240187–24
Following any idle bus state (Ti), addresses are non-pipelined. Within non-pipelined bus cycles, NA
Y
is only sampled
during wait states. Therefore, to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipe-
lined cycle with at least one wait state (Cycle 2 above).
Figure 5.9. Transitioning to Pipelined Address During Burst of Bus Cycles
51
相關(guān)PDF資料 |
PDF描述 |
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| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
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