- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377495 > intel M80C186 (Intel Corp.) CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) PDF資料下載
參數(shù)資料
| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 5/59頁 |
| 文件大小： | 529K |
| 代理商： | INTEL M80C186 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
M80C186
Table 1. M80C186 Pin Description
(Continued)
Symbol
BHE
PGA
64
QFP
14
Type
O
Name and Function
The BHE (Bus High Enable) signal is analogous to A0 in that
it is used to enable data on to the most significant half of the
data bus, pins D15–D8. BHE will be LOW during T
1
when the
upper byte is transferred and will remain LOW through T
3
AND T
W
. BHE does not need to be latched. BHE will float
during HOLD.
In Enhanced Mode, BHE will also be used to signify DRAM
refresh cycles. A refresh cycle is indicated by BHE and A0
being HIGH.
BHE and A0 Encodings
BHE Value
A0 Value
0
0
0
1
Function
Word Transfer
Byte Transfer on upper half
of data bus (D15–D8)
Byte Transfer on lower half
of data bus (D
7
–D
0
)
Refresh
1
0
1
1
ALE/QS0
61
17
O
Address Latch Enable/Queue Status 0 is provided by the
M80C186 to latch the address. ALE is active HIGH.
Addresses are guaranteed to be valid on the trailing edge of
ALE. The ALE rising edge is generated off the rising edge of
the CLKOUT immediately preceding T
1
of the associated bus
cycle, effectively one-half clock cycle earlier than in the
standard M8086. The trailing edge is generated off the
CLKOUT rising edge in T
1
as in the M8086. Note that ALE is
never floated.
Write Strobe/Queue Status 1 indicates that the data on the
bus is to be written into a memory or an I/O device. WR is
active for T
2
, T
3
, and T
W
of any write cycle. It is active LOW,
and floats during ‘‘HOLD.’’ It is driven HIGH for one clock
during Reset, and then floated. When the M80C186 is in
queue status mode, the ALE/QS0 and WR/QS1 pins provide
information about processor/instruction queue interaction.
QS1
QS0
0
0
0
1
WR/QS1
63
15
O
Queue Operation
No queue operation
First opcode byte fetched
from the queue
Subsequent byte fetched
from the queue
Empty the queue
1
1
1
0
RD/QSMD
62
16
O
Read Strobe indicates that the M80C186 is performing a
memory or I/O read cycle. RD is active LOW for T
2
, T
3
, and
T
W
of any read cycle. It is guaranteed not to go LOW in T
2
until after the Address Bus is floated. RD is active LOW, and
floats during ‘‘HOLD’’. RD is driven HIGH for one clock
during Reset, and then the output driver is floated. A weak
internal pull-up mechanism of the RD line holds it HIGH when
the line is not driven. During RESET the pin is sampled to
determine whether the M80C186 should provide ALE, WR
and RD, or if the Queue-Status should be provided. RD
should be connected to GND to provide Queue-Status data.
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| intel Pentium CPU | 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動模塊處理器) |
| intel Pentium II processor | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| INTEL386 CXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| INTEL386 CXSB | Low-Voltage, 32-Bit, Fully Static Embedded Microprocessor(低電壓32位完全靜態(tài)嵌入式微處理器) |
| intel386 DX | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEN I/O PCB | 制造商:Sliger Designs, Inc. 功能描述:I/O PCB - Bulk |
| INTEN LED PCB | 制造商:Sliger Designs, Inc. 功能描述:LED PCB - Bulk |
| INTEN-1-PROTO | 制造商:Sliger Designs, Inc. 功能描述:QUANTITY TWO PROTO TYPE SHEET METAL - Bulk |
| INTENSI-FI | 制造商:BOARDCOM 制造商全稱:Broadcom Corporation. 功能描述:DRAFT-802.11n PRODUCT FAMILY |
| INTER0.5 | 制造商:POWERDATA TECHNOLOGIES 功能描述:LEAD WIELAND TO WIELAND 0.5M |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。