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參數(shù)資料
| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
ALT:
The ALT bit determines which of two MAX COUNT
registers is used for count comparison. If ALT
e
0,
register A for that timer is always used, while if ALT
e
1, the comparison will alternate between register
A and register B when each maximum count is
reached. This alternation allows the user to change
one MAX COUNT register while the other is being
used, and thus provides a method of generating
non-repetitive waveforms. Square waves and pulse
outputs of any duty cycle are a subset of available
signals obtained by not changing the final count reg-
isters. The ALT bit also determines the function of
the timer output pin. If ALT is zero, the output pin will
go LOW for one clock, the clock after the maximum
count is reached. If ALT is one, the output pin will
reflect the current MAX COUNT register being used
(0/1 for B/A).
CONT:
Setting the CONT bit causes the associated timer to
run continuously, while resetting it causes the timer
to halt upon maximum count. If COUNT
e
0 and
ALT
e
1, the timer will count to the MAX COUNT
register A value, reset, count to the register B value,
reset, and halt.
EXT:
The external bit selects between internal and exter-
nal clocking for the timer. The external signal may
be asynchronous with respect to the M80C186
clock. If this bit is set, the timer will count LOW-to-
HIGH transitions on the input pin. If cleared, it will
count an internal clock while using the input pin for
control. In this mode, the function of the external pin
is defined by the RTG bit. The maximum input to
output transition latency time may be as much as 6
clocks. However, clock inputs may be pipelined as
closely together as every 4 clocks without losing
clock pulses.
P:
The prescaler bit is ignored unless internal clocking
has been selected (EXT
e
0). If the P bit is a zero,
the timer will count at one-fourth the internal CPU
clock rate. If the P bit is a one, the output of timer 2
will be used as a clock for the timer. Note that the
user must initialize and start timer 2 to obtain the
prescaled clock.
RTG:
Retrigger bit is only active for internal clocking (EXT
e
0). In this case it determines the control function
provided by the input pin.
If RTG
e
0, the input level gates the internal clock
on and off. If the input pin is HIGH, the timer will
count; if the input pin is LOW, the timer will hold its
value. As indicated previously, the input signal may
be asynchronous with respect to the M80C186
clock.
When RTG
e
1, the input pin detects LOW-to-HIGH
transitions. The first such transition starts the timer
running, clearing the timer value to zero on the first
clock, and then incrementing thereafter. Further
transitions on the input pin will again reset the timer
to zero, from which it will start counting up again. If
CONT
e
0, when the timer has reached maximum
count, the EN bit will be cleared, inhibiting further
timer activity.
EN:
The enable bit provides programmer control over
the timer’s RUN/HALT status. When set, the timer is
enabled to increment subject to the input pin con-
straints in the internal clock mode (discussed previ-
ously). When cleared, the timer will be inhibited from
counting. All input pin transistions during the time EN
is zero will be ignored. If CONT is zero, the EN bit is
automatically cleared upon maximum count.
INH:
The inhibit bit allows for selective updating of the
enable (EN) bit. If INH is a one during the write to the
mode/control word, then the state of the EN bit will
be modified by the write. If INH is a zero during the
write, the EN bit will be unaffected by the operation.
This bit is not stored; it will always be a 0 on a read.
INT:
When set, the INT bit enables interrupts from the
timer, which will be generated on every terminal
count. If the timer is configured in dual MAX COUNT
register mode, an interrupt will be generated each
time the value in MAX COUNT register A is reached,
and each time the value in MAX COUNT register B is
reached. If this enable bit is cleared after the inter-
rupt request has been generated, but before a pend-
ing interrupt is serviced, the interrupt request will still
be in force. (The request is latched in the Interrupt
Controller).
MC:
The Maximum Count bit is set whenever the timer
reaches its final maximum count value. If the timer is
configured in dual MAX COUNT register mode, this
bit will be set each time the value in MAX COUNT
register A is reached, and each time the value in
MAX COUNT register B is reached. This bit is set
30
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