參數(shù)資料
型號(hào)： intel M80C186
廠商： Intel Corp.
英文描述： CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器)
中文描述： CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器）
文件頁(yè)數(shù)： 45/59頁(yè)
文件大小： 529K
代理商： INTEL M80C186
M80C186
DC CHARACTERISTICS
(Over Specified Operating Conditions) (Continued)
Symbol
Parameter
Min
b
0.5
Max
Units
Comments
V
CLI
V
CHI
C
IN
C
IO
Clock Input Low Voltage (X1)
0.6
V
Clock Input High Voltage (X1)
3.9
V
CC
10
V
Input Capacitance
pF
@
1 MHz
(2)
I/O Capacitance
20
pF
@
1 MHz
(2)
NOTES:
1. Pins being floated during HOLD or by invoking the ONCE Mode.
2. Characterization conditions are a) Frequency
e
1 MHz; b) Unmeasured pins at GND; V
IN
at
a
5.0V or
a
0.45V.
3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.
4. RD/QSMD, UCS, MSC0/PEREQ, MCSL/ERROR, and TEST/BUSY pins have internal pullup devices that are active at
RESET. Excessive loading on these pins can cause the M80C186 to go into undesired modes of operation (e.g., Queue
Status, ONCE) upon RESET.
PIN TIMINGS
AC CHARACTERISTICS
(Over Specified Operating Conditions)
All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
L
e
50–200 pF (10 MHz) and C
L
e
50–100 pF (12.5 MHz).
For AC tests, input V
IL
e
0.45V and V
IN
e
2.4V except at X
1
where V
IH
e
V
CC
b
0.5V.
M80C186-10
Symbol
Parameter
M80C186-12
Unit
Comments
Min
Max
Min
Max
M80C186 TIMING REQUIREMENTS
T
DVCL
T
CLDX
T
ARYCH
Data In Setup (A/D)
20
20
ns
Data In Hold (A/D)
5
5
ns
ARDY Resolution
Transition Setup Time
(1)
20
20
ns
T
ARYLCL
Asynchronous Ready
(ARDY) Setup Time
30
30
ns
T
CLARX
T
ARYCHL
T
SRYCL
ARDY Active Hold Time
15
15
ns
ARDY Inactive Hold Time
15
15
ns
Synchronous Ready (SRDY)
Transition Setup Time
20
20
ns
T
CLSRY
T
HVCL
T
INVCH
SRDY Transition Hold Time
HOLD Setup
(1)
20
20
ns
20
20
ns
INTR, NMI, TEST, TMR IN
Setup Time
(1)
DRQ0, DRQ1, Setup Time
(1)
20
20
ns
T
INVCL
M80C186 MASTER INTERFACE TIMING RESPONSES
20
20
ns
T
CLAV
T
CLAX
T
CLAZ
T
CHCZ
T
CHCV
Address Valid Delay
5
50
5
37
ns
C
L
e
50 pF–200 pF
all outputs
(except T
CLTMV
)
@
10 MHz
Address Hold
0
0
ns
Address Float Delay
T
CLAX
30
T
CLAX
25
ns
Command Lines Float Delay
40
33
ns
Command Lines Valid
Delay (after Float)
45
37
ns
C
L
e
50 pF–100 pF
all outputs
@
12.5 MHz
T
LHLL
T
CHLH
T
CHLL
ALE Width (min)
T
CLCL
b
30
T
CLCL
b
30
ns
ALE Active Delay
30
25
ns
ALE Inactive Delay
30
25
ns
45
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