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| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 33/59頁 |
| 文件大小： | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
270500–22
Figure 22. Fully Nested (Direct) Mode Interrupt
Controller Connections
Special Fully Nested Mode
This mode is entered by setting the SFNM bit in
INT0 or INT1 control register. It enables complete
nestability with external M82C59A masters. Normal-
ly, an interrupt request from an interrupt source will
not be recognized unless the in-service bit for that
source is reset. If more than one interrupt source is
connected to an external interrupt controller, all of
the interrupts will be funneled through the same
M80C186 interrupt request pin. As a result, if the
external interrupt controller receives a higher-priority
interrupt, its interrupt will not be recognized by the
M80C186 controller until the M80C186 in-service bit
is reset. In special fully nested mode, the M80C186
interrupt controller will allow interrupts from an exter-
nal pin regardless of the state of the in-service bit for
an interrupt source in order to allow multiple inter-
rupts from a single pin. An in-service bit will continue
to be set, however, to inhibit interrupts from other
lower-priority M80C186 interrupt sources.
Special procedures should be followed when reset-
ting IS bits at the end of interrupt service routines.
Software polling of the external master’s IS register
is required to determine if there is more than one bit
set. If so, the IS bit in the M80C186 remains active
and the next interrupt service routine is entered.
Operation in a Polled Environment
The controller may be used in a polled mode if inter-
rupts are undesirable. When polling, the processor
disables interrupts and then polls the interrupt con-
troller whenever it is convenient. Polling the interrupt
controller is accomplished by reading the Poll Word
(Figure 32). Bit 15 in the poll word indicates to the
processor that an interrupt of high enough priority is
requesting service. Bits 0–4 indicate to the proces-
sor the type vector of the highest-priority source re-
questing service. Reading the Poll Word causes the
In-Service bit of the highest priority source to be set.
It is desirable to be able to read the Poll Word infor-
mation without guaranteeing service of any pending
interrupt, i.e., not set the indicated in-service bit. The
M80C186 provides a Poll Status Word in addition to
the conventional Poll Word to allow this to be done.
Poll Word information is duplicated in the Poll Status
Word, but reading the Poll Status Word does not set
the associated in-service bit. These words are locat-
ed in two adjacent memory locations in the register
file.
Master Mode Features
Programmable Priority
The user can program the interrupt sources into any
of eight different priority levels. The programming is
done by placing a 3-bit priority level (0–7) in the con-
trol register of each interrupt source. (A source with
a priority level of 4 has higher priority over all priority
levels from 5 to 7. Priority registers containing values
lower than 4 have greater priority). All interrupt
sources have preprogrammed default priority levels
(see Table 4).
If two requests with the same programmed priority
level are pending at once, the priority ordering
scheme shown in Table 4 is used. If the serviced
interrupt routine reenables interrupts, it allows other
requests to be serviced.
End-of-Interrupt Command
The end-of-interrupt (EOI) command is used by the
programmer to reset the In-Service (IS) bit when an
interrupt service routine is completed. The EOI com-
mand is issued by writing the proper pattern to the
EOI register. There are two types of EOI commands,
specific and nonspecific. The nonspecific command
does not specify which IS bit is reset. When issued,
the interrupt controller automatically resets the IS bit
of the highest priority source with an active service
routine. A specific EOI command requires that the
programmer send the interrupt vector type to the in-
terrupt controller indicating which source’s IS bit is
to be reset. This command is used when the fully
nested structure has been disturbed or the highest
priority IS bit that was set does not belong to the
service routine in progress.
Trigger Mode
The four external interrupt pins can be programmed
in either edge- or level-trigger mode. The control
register for each external source has a level-trigger
mode (LTM) bit. All interrupt inputs are active HIGH.
In the edge sense mode or the level-trigger mode,
the interrupt request must remain active (HIGH) until
the interrupt request is acknowledged by the
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