參數(shù)資料
型號(hào)： intel M80C186
廠商： Intel Corp.
英文描述： CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器)
中文描述： CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器）
文件頁(yè)數(shù)： 28/59頁(yè)
文件大?。?/td> 529K
代理商： INTEL M80C186
M80C186
DMA Acknowledge
No explicit DMA acknowledge pulse is provided.
Since both source and destination pointers are
maintained, a read from a requesting source, or a
write to a requesting destination, should be used as
the DMA acknowledge signal. Since the chip-select
lines can be programmed to be active for a given
block of memory or I/O space, and the DMA point-
ers can be programmed to point to the same given
block, a chip-select line could be used to indicate a
DMA acknowledge.
DMA Priority
The DMA channels may be programmed such that
one channel is always given priority over the other,
or they may be programmed such as to alternate
cycles when both have DMA requests pending. DMA
cycles always have priority over internal CPU cycles
except between locked memory accesses or word
accesses to odd memory locations; however, an ex-
ternal bus hold takes priority over an internal DMA
cycle. Because an interrupt request cannot suspend
a DMA operation and the CPU cannot access mem-
ory during a DMA cycle, interrupt latency time will
suffer during sequences of continuous DMA cycles.
An NMI request, however, will cause all internal
DMA activity to halt. This allows the CPU to quickly
respond to the NMI request.
DMA Programming
DMA cycles will occur whenever the ST/STOP bit of
the Control Register is set. If synchronized transfers
are programmed, a DRQ must also have been gen-
erated. Therefore the source and destination trans-
fer pointers, and the transfer count register (if used)
must be programmed before this bit is set.
Each DMA register may be modified while the chan-
nel is operating. If the CHG/NOCHG bit is cleared
when the control register is written, the ST/STOP bit
of the control register will not be modified by the
write. If multiple channel registers are modified, it is
recommended that a LOCKED string transfer be
used to prevent a DMA transfer from occurring be-
tween updates to the channel registers.
DMA Channels and Reset
Upon RESET, the DMA channels will perform the
following actions:
#
The Start/Stop bit for each channel will be reset
to STOP.
#
Any transfer in progress is aborted.
TIMERS
The M80C186 provides three internal 16-bit pro-
grammable timers (see Figure 19). Two of these are
highly flexible and are connected to four external
pins (2 per timer). They can be used to count exter-
nal events, time external events, generate nonrepet-
itive waveforms, etc. The third timer is not connect-
ed to any external pins, and is useful for real-time
coding and time delay applications. In addition, this
third timer can be used as a prescaler to the other
two, or as a DMA request source.
270500–10
Figure 19. Timer Block Diagram
28
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