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參數(shù)資料
| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 32/59頁 |
| 文件大?。?/td> | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
Interrupt Controller Modes of
Operation
The basic modes of operation of the interrupt con-
troller in master mode are similar to the M82C59A.
The interrupt controller responds indentically to in-
ternal interrupts in all three modes: the difference is
only in the interpretation of function of the four exter-
nal interrupt pins. The interrupt controller is set into
one of these three modes by programming the cor-
rect bits in the INT0 and INT1 control registers. The
modes of interrupt controller operation are as fol-
lows:
Fully Nested Mode
When in the fully nested mode four pins are used as
direct interrupt requests as in Figure 22. The vectors
for these four inputs are generated internally. An in-
service bit is provided for every interrupt source. If a
lower-priority device requests an interrupt while the
in service bit (IS) is set, no interrupt will be generat-
ed by the interrupt controller. In addition, if another
interrupt request occurs from the same interrupt
source while the in-service bit is set, no interrupt will
be generated by the interrupt controller. This allows
interrupt service routines to operate with interrupts
enabled without being themselves interrupted by
lower-priority interrupts. Since interrupts are en-
abled, higher-priority interrupts will be serviced.
When a service routine is completed, the proper IS
bit must be reset by writing the proper pattern to the
EOI register. This is required to allow subsequent
interrupts from this interrupt source and to allow
servicing of lower-priority interrupts. An EOI com-
mand is issued at the end of the service routine just
before the issuance of the return from interrupt in-
struction. If the fully nested structure has been up-
held, the next highest-priority source with its IS bit
set is then serviced.
Cascade Mode
The M80C186 has four interrupt pins and two of
them have dual functions. In the fully nested mode
the four pins are used as direct interrupt inputs and
the corresponding vectors are generated internally.
In the cascade mode, the four pins are configured
into interrupt input-dedicated acknowledge signal
pairs. The interconnection is shown in Figure 23.
INT0 is an interrupt input interfaced to an M82C59A,
while INT2/INTA0 serves as the dedicated interrupt
acknowledge signal to that peripheral. The same is
true for INT1 and INT3/INTA1. Each pair can selec-
tively be placed in the cascade or non-cascade
mode by programming the proper value into INT0
and INT1 control registers. The use of the dedicated
acknowledge signals eliminates the need for the use
of external logic to generate INTA and device select
signals.
The primary cascade mode allows the capability to
serve up to 128 external interrupt sources through
the use of external master and slave M82C59As.
Three levels of priority are created, requiring priority
resolution in the M80C186 interrupt controller, the
master M82C59As, and the slave M82C59As. If an
external interrupt is serviced, one IS bit is set at
each of these levels. When the interrupt service rou-
tine is completed, up to three end-of-interrupt com-
mands must be issued by the programmer.
270500–11
Figure 21. Interrupt Controller Block Diagram
32
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