參數(shù)資料
型號(hào)： intel M80C186
廠商： Intel Corp.
英文描述： CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器)
中文描述： CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器）
文件頁(yè)數(shù)： 4/59頁(yè)
文件大?。?/td> 529K
代理商： INTEL M80C186
M80C186
Table 1. M80C186 Pin Description
(Continued)
Symbol
PGA
QFP
Type
Name and Function
TMR IN 1
TMR IN 0,
20
21
58
57
I
I
Timer Inputs are used either as clock or control signals,
depending upon the programmed timer mode. These inputs
are active HIGH (or LOW-to-HIGH transitions are counted) and
internally synchronized.
TMR OUT 0,
TMR OUT 1
23
22
56
55
O
O
Timer outputs are used to provide single pulse or continous
waveform generation, depending upon the timer mode
selected.
DRQ1
DRQ0
18
19
59
60
I
I
DMA Request is driven HIGH by an external device when it
desires that a DMA channel (Channel 0 or 1) perform a
transfer. These signals are active HIGH, level-triggered, and
internally synchronized.
NMI
46
32
I
Non-Maskable Interrupt is an edge-triggered input which
causes a type 2 interrupt. NMI is not maskable internally. A
transition from a LOW to HIGH initiates the interrupt at the
next instruction boundary. NMI is latched internally. An NMI
duration of one clock or more will guarantee service. This input
is internally synchronized.
INT0, INT1
INT2/INTA0
INT3/INTA1
45, 44
42
41
33, 34
36
37
I/O
I/O
I
Maskable Interrupt Requests can be requested by activating
one of these pins. When configured as inputs, these pins are
active HIGH. Interrupt Requests are synchronized internally.
INT2 and INT3 may be configured via software to provide
active-LOW interrupt-acknowledge output signals. All interrupt
inputs may be configured via software to be either edge- or
level-triggered. To ensure recognition, all interrupt requests
must remain active until the interrupt is acknowledged. When
slave mode is selected, the function of these pins changes
(see Interrupt Controller section of this data sheet).
A19/S6,
A18/S5,
A16/S3
A17/S4,
65
66
68
67
13
12
10
11
O
O
O
O
Address Bus Outputs (16–19) and Bus Cycle Status (3–6)
reflect the four most significant address bits during T
1
. These
signals are active HIGH. During T
2
, T
3
, T
W
, and T
4
, status
information is available on these lines as encoded below:
Low
High
S6
Processor Cycle
DMA Cycle
S3, S4, and S5 are defined as LOW during T
2
–T
4
.
Address/Data Bus (0–15) signals constitute the time
multiplexed memory or I/O address (T
1
) and data (T
2
, T
3
, T
W
,
and T
4
) bus. The
bus is active HIGH. A
0
is analogous to BHE for the lower byte
of the data bus, pins D
7
through D
0
. It is LOW during T
1
when
a byte is to be transferred onto the lower portion of the bus in
memory or I/O operations.
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
3
5
7
10
12
14
16
2
4
6
8
11
13
15
17
9
7
5
3
68
66
64
62
8
6
4
2
67
65
63
61
I/O
4
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