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| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 31/59頁 |
| 文件大小： | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
regardless of the timer’s interrupt-enable bit. The
MC bit gives the user the ability to monitor timer
status through software instead of through inter-
rupts.
Programmer intervention is required to clear this bit.
RIU:
The Register In Use bit indicates which MAX
COUNT register is currently being used for compari-
son to the timer count value. A zero value indicates
register A. The RIU bit cannot be written, i.e., its
value is not affected when the control register is writ-
ten. It is always cleared when the ALT bit is zero.
Not all mode bits are provided for timer 2. Certain
bits are hardwired as indicated below:
ALT
e
0, EXT
e
0, P
e
0, RTG
e
0, RIU
e
0
Count Registers
Each of the three timers has a 16-bit count register.
The current contents of this register may be read or
written by the processor at any time. If the register is
written into while the timer is counting,the new value
will take effect in the current count cycle.
Max Count Registers
Timers 0 and 1 have two MAX COUNT registers,
while timer 2 has a single MAX COUNT register.
These contain the number of events the timer will
count. In timers 0 and 1, the MAX COUNT register
used can alternate between the two max count val-
ues whenever the current maximum count is
reached. The condition which causes a timer to re-
set is equivalent between the current count value
and the max count being used. This means that if
the count is changed to be above the max count
value, or if the max count value is changed to be
below the current value, the timer will not reset to
zero, but rather will count to its maximum value,
‘‘wrap around’’ to zero, then count until the max
count is reached.
Timers and Reset
Upon RESET, the Timers will perform the following
actions:
#
All EN (Enable) bits are reset preventing timer
counting.
#
All SEL (Select) bits are reset to zero. This se-
lects MAX COUNT register A, resulting in the
Timer Out pins going HIGH upon RESET.
INTERRUPT CONTROLLER
The M80C186 can receive interrupts from a number
of sources, both internal and external. The internal
interrupt controller serves to merge these requests
on a priority basis, for individual service by the CPU.
Internal interrupt sources (Timers and DMA chan-
nels) can be disabled by their own control registers
or by mask bits within the interrupt controller. The
M80C186 interrupt controller has its own control
register that set the mode of operation for the con-
troller.
The interrupt controller will resolve priority among
requests that are pending simultaneously. Nesting is
provided so interrupt service routines for lower priori-
ty interrupts may themselves be interrupted by high-
er priority interrupts. A block diagram of the interrupt
controller is shown in Figure 21.
The M80C186 has a special slave mode in which the
internal interrupt controller acts as a slave to an ex-
ternal master. The controller is programmed into this
mode by setting bit 14 in the peripheral control block
relocation register. (See Slave Mode section.)
MASTER MODE OPERATION
Interrupt Controller External Interface
For external interrupt sources, five dedicated pins
are provided. One of these pins is dedicated to NMI,
non-maskable interrupt. This is typically used for
power-fail interrupts, etc. The other four pins may
function either as four interrupt input lines with inter-
nally generated interrupt vectors, as an interrupt line
and an interrupt acknowledge line (called the ‘‘cas-
cade mode’’) along with two other input lines with
internally generated interrupt vectors, or as two in-
terrupt input lines and two dedicated interrupt ac-
knowledge output lines. When the interrupt lines are
configured in cascade mode, the M80C186 interrupt
controller will not generate internal interrupt vectors.
External sources in the cascade mode use external-
ly generated interrupt vectors. When an interrupt is
acknowledged, two INTA cycles are initiated and the
vector is read into the M80C186 on the second cy-
cle. The capability to interface to external M82C59A
programmable interrupt controllers is thus provided
when the inputs are configured in cascade mode.
31
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