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參數(shù)資料
| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 26/59頁 |
| 文件大?。?/td> | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
15
14
13
12
11
10
9
8
7
6
5
4
T
D
R
Q
3
2
1
0
M/
IO
X
e
DON’T CARE.
DESTINATION
DEC
M/
IO
SOURCE
DEC
TC
INT
SYN
P
X
CHG/
NOCHG STOP
ST/
B/
W
INC
INC
Figure 17. DMA Control Register
DMA Channel Control Word Register
Each DMA Channel Control Word determines the
mode of operation for the particular M80C186 DMA
channel. This register specifies:
#
the mode of synchronization;
#
whether bytes or words will be transferred;
#
whether interrupts will be generated after the last
transfer;
#
whether DMA activity will cease after a pro-
grammed number of DMA cycles;
#
the relative priority of the DMA channel with re-
spect to the other DMA channel;
#
whether the source pointer will be incremented,
decremented, or maintained constant after each
transfer;
#
whether the source pointer addresses memory or
I/O space;
#
whether the destination pointer will be increment-
ed, decremented, or maintained constant after
each transfer; and
#
whether the destination pointer will address
memory or I/O space.
The DMA channel control registers may be changed
while the channel is operating. However, any chang-
es made during operation will affect the current DMA
transfer.
DMA Control Word Bit Descriptions
B/W:
Byte/Word (0/1) Transfers.
ST/STOP:
Start/stop (1/0) Channel.
CHG/NOCHG:
Change/Do
ST/STOP bit. If this bit is set when
writing to the control word, the
ST/STOP bit will be programmed
by the write to the control word. If
this bit is cleared when writing the
control word, the ST/STOP bit will
not be altered. This bit is not
stored; it will always be a 0 on
read.
not
change
(1/0)
INT:
Enable
Transfer Count termination.
Interrupts
to
CPU
on
TC:
If set, DMA will terminate when
the contents of the Transfer Count
register reach zero. The ST/STOP
bit will also be reset at this point if
TC is set. If this bit is cleared, the
DMA unit will decrement the trans-
fer count register for each DMA
cycle, but the DMA transfer will
not stop when the contents of the
TC register reach zero.
SYN
00 No synchronization.
NOTE:
When unsynchronized transfers
are specified, the TC bit will be ig-
nored and the ST bit will be
cleared upon the transfer count
reaching zero, stopping the chan-
nel.
(2 bits)
01 Source synchronization.
10 Destination synchronization.
11 Unused.
SOURCE:INC
Increment source pointer by 1 or 2
(depends on B/W) after each
transfer.
M/IO Source pointer is in M/IO space
(1/0).
DEC Decrement source pointer by 1 or
2 (depends on B/W) after each
transfer.
DEST:
INC Increment destination pointer by 1
or 2 (B/W) after each transfer.
M/IO Destination pointer is in M/IO
space (1/0).
DEC Decrement destination pointer by
1 or 2 (depending on B/W) after
each transfer.
P
Channel priorityDrelative to other
channel.
0 low priority.
1 high priority.
Channels will alternate cycles if
both set at same priority level.
TDRQ
0: Disable DMA requests from tim-
er 2.
1: Enable DMA requests from tim-
er 2.
Bit 3
Bit 3 is not used.
26
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