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參數(shù)資料
| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 35/59頁 |
| 文件大?。?/td> | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
sponding to a particular source serves to mask the
source from generating interrupts. These mask bits
are the exact same bits which are used in the indi-
vidual control registers; programming a mask bit us-
ing the mask register will also change this bit in the
individual control registers, and vice versa.
OFFSET
INT3 CONTROL REGISTER
3EH
INT2 CONTROL REGISTER
3CH
INT1 CONTROL REGISTER
3AH
INT0 CONTROL REGISTER
38H
DMA 1 CONTROL REGISTER
36H
DMA 0 CONTROL REGISTER
34H
TIMER CONTROL REGISTER
32H
INTERRUPT STATUS REGISTER
30H
INTERRUPT REQUEST REGISTER
2EH
IN-SERVICE REGISTER
2CH
PRIORITY MASK REGISTER
2AH
MASK REGISTER
28H
POLL STATUS REGISTER
26H
POLL REGISTER
24H
EOI REGISTER
22H
Figure 24. Interrupt Controller Registers
(Master Mode)
Priority Mask Register
This register is used to mask all interrupts below par-
ticular interrupt priority levels. The format of this reg-
ister is shown in Figure 26. The code in the lower
three bits of this register inhibits interrupts of priority
lower (a higher priority number) than the code speci-
fied. For example, 100 written into this register
masks interrupts of level five (101), six (110), and
seven (111). The register is reset to seven (111)
upon RESET so no interrupts are masked due to
priority number.
Interrupt Status Register
This register contains general interrupt controller
status information. The format of this register is
shown in Figure 27. The bits in the status register
have the following functions:
DHLT: DMA Halt Transfer; setting this bit halts all
DMA transfers. It is automatically set when-
ever a non-maskable interrupt occurs, and it
is reset when an IRET instruction is execut-
ed. The purpose of this bit is to allow prompt
service of all non-maskable interrupts. This
bit may also be set by the programmer.
IRTx: These three bits represent the individual tim-
er interrupt request bits. These bits are used
to differentiate the timer interrupts, since the
timer IR bit in the interrupt request register is
the ‘‘OR’’ function of all timer interrupt re-
quest. Note that setting any one of these
three bits initiates an interrupt request to the
interrupt controller.
15
0
14
0
10
0
9
0
8
0
7
6
5
I1
4
I0
3
2
1
0
0
#
#
#
13
12
D1
D0
TMR
Figure 25. In-Service, Interrupt Request, and Mask Register Formats
15
0
14
0
3
0
2
1
0
#
#
#
#
#
#
#
#
#
PRM2 PRM1 PRM0
Figure 26. Priority Mask Register Format
15
14
0
7
0
6
0
5
0
4
0
3
0
2
1
0
DHLT
#
#
#
#
#
IRT2
IRT1
IRT0
Figure 27. Interrupt Status Register Format (Master Mode)
35
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