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| 型號： | intel M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| 中文描述： | CHMOS高集成的16位微處理器（CHMOS高集成16位微處理器） |
| 文件頁數(shù)： | 27/59頁 |
| 文件大?。?/td> | 529K |
| 代理商： | INTEL M80C186 |
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M80C186
If both INC and DEC are specified for the same
pointer, the pointer will remain constant after each
cycle.
DMA Destination and Source Pointer
Registers
Each DMA channel maintains a 20-bit source and a
20-bit destination pointer. Each of these pointers
takes up two full 16-bit registers in the peripheral
control block. The lower four bits of the upper regis-
ter contain the upper four bits of the 20-bit physical
address (see Figure 18). These pointers may be indi-
vidually incremented or decremented after each
transfer. If word transfers are performed the pointer
is incremented or decremented by two. Each pointer
may point into either memory or I/O space. Since
the DMA channels can perform transfers to or from
odd addresses, there is no restriction on values for
the pointer registers. Higher transfer rates can be
obtained if all word transfers are performed to even
addresses, since this will allow data to be accessed
in a single memory access.
DMA Transfer Count Register
Each DMA channel maintains a 16-bit transfer count
register (TC). This register is decremented after ev-
ery DMA cycle, regardless of the state of the TC bit
in the DMA Control Register. If the TC bit in the DMA
control word is set or if unsynchronized transfers are
programmed, however, DMA activity will terminate
when the transfer count register reaches zero.
DMA Requests
Data transfers may be either source or destination
synchronized, that is either the source of the data or
the destination of the data may request the data
transfer. In addition, DMA transfers may be unsyn-
chronized; that is, the transfer will take place contin-
ually until the correct number of transfers has oc-
curred. When source or unsynchronized transfers
are performed, the DMA channel may begin another
transfer immediately after the end of a previous
DMA transfer. This allows a complete transfer to
take place every 2 bus cycles or eight clock cycles
(assuming no wait states). No prefetching occurs
when destination synchronization is performed, how-
ever. Data will not be fetched from the source ad-
dress until the destination device signals that it is
ready to receive it. When destination synchronized
transfers are requested, the DMA controller will re-
linquish control of the bus after every transfer. If no
other bus activity is initiated, another DMA cycle will
begin after two processor clocks. This is done to
allow the destination device time to remove its re-
quest if another transfer is not desired. Since the
DMA controller will relinquish the bus, the CPU can
initiate a bus cycle. As a result, a complete bus cycle
will often be inserted between destination synchro-
nized transfers. These lead to the maximum DMA
transfer rates shown in Table 14.
Table 14. Maximum DMA
Transfer Rates
Type of
Synchronization
Selected
CPU Running
CPU Halted
Unsynchronized
Source Synch
Destination Synch
2.5MBytes/sec
2.5MBytes/sec
1.7MBytes/sec
2.5MBytes/sec
2.5MBytes/sec
2.0MBytes/sec
HIGHER
REGISTER
ADDRESS
XXX
XXX
XXX
A19–A16
LOWER
REGISTER
ADDRESS
A15–A12
A11–A8
A7–A4
A3–A0
15
0
XXX
e
DON’T CARE
Figure 18. DMA Memory Pointer Register Format
27
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