參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 41/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
APPENDIX A
COMPATIBILITY BETWEEN
THE M80287 AND THE M8087
The M80286/M80287 operating in Real-Address
mode will execute M8086/M8087 programs without
major modification. However, because of differences
in the handling of numeric exceptions by the
M80287 NPX and the M8087 NPX, exception-han-
dling routines may need to be changed.
This appendix summarizes the differences between
the M80287 NPX and the M8087 NPX, and provides
details showing how M8086/M8087 programs can
be ported to the M80286/M80287.
1. The NPX signals exceptions through a dedicated
ERROR line to the M80286. The NPX error signal
does not pass through an interrupt controller (the
M8087 INT signal does). Therefore, any interrupt-
controller-oriented instructions in numeric excep-
tion handlers for the M8086/M8087 should be de-
leted.
2. The M8087 instructions FENI/FNENI and FDISI/
FNDISI perform no useful function in the M80287.
If the M80287 encounters one of these opcodes
in its instruction stream, the instruction will effec-
tively be ignoredDnone of the M80287 internal
states will be updated. While M8086/M8087 con-
taining these instructions may be executed on the
M80286/M80287, it is unlikely that the exception-
handling routines containing these instructions
will be completely portable to the M80287.
3. Interrupt vector 16 must point to the numeric ex-
ception handling routine.
4. The ESC instruction address saved in the
M80287 includes any leading prefixes before the
ESC opcode. The corresponding address saved
in the M8087 does not include leading prefixes.
5. In Protected-Address mode, the format of the
M80287’s saved instruction and address pointers
is different than for the M8087. The instruction
opcode is not saved in Protected modeDexcep-
tion handlers will have to retrieve the opcode from
memory if needed.
6. Interrupt 7 will occur in the M80286 when execut-
ing
ESC
instructions
switched) or EM (emulation) of the M80286 MSW
with
either
TS
(task
set (TS
e
1 or EM
e
1). If TS is set, then a WAIT
instruction will also cause interrupt 7. An excep-
tion
handler
should
M80286/M80287 code to handle these situations.
be
included
in
7. Interrupt 9 will occur if the second or subsequent
words of a floating-point operand fall outside a
segment’s size. Interrupt 13 will occur if the start-
ing address of a numeric operand falls outside a
segment’s size. An exception handler should be
included in M80286/M80287 code to report these
programming errors.
8. Except for the processor control instructions, all
of the M80287 numeric instructions are automati-
cally synchronized by the M80286 CPUDthe
M80286 automatically tests the BUSY line from
the M80287 to ensure that the M80287 has com-
pleted its previous instruction before executing
the next ESC instruction. No explicit WAIT instruc-
tions are required to assure this synchronization.
For the M8087 used with M8086 and M8088 proc-
essors, explicit WAITs are required before each
numeric instruction to ensure synchronization. Al-
though M8086/M8087 programs having explicit
WAIT instructions will execute perfectly on the
M80286/M80287
without
WAIT instructions are unnecessary.
reassembly,
these
9. Since the M80287 does not require WAIT instruc-
tions
before
each
numeric
ASM286 assembler does not automatically gener-
ate these WAIT instructions. The ASM86 assem-
bler, however, automatically precedes every ESC
instruction with a WAIT instruction. Although nu-
meric routines generated using the ASM86 as-
sembler will generally execute correctly on the
M80286/M80287,
reassembly
may result in a more compact code image.
instruction,
the
using
ASM286
The processor control instructions for the M80287
may be coded using either a WAIT or No-WAIT
form of mnemonic. The WAIT forms of these in-
structions cause ASM286 to precede the ESC in-
struction with a CPU WAIT instruction, in the iden-
tical manner as does ASM86.
A-1
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