參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 27/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
3.4.3 BUS CYCLES OF MIXED TYPE
When the i387 NPX bus logic is in the T
RS
state, it
distinguishes between nonpipelined and pipelined
cycles according to the behavior of ADS and
READY. In a nonpipelined cycle, only READY is acti-
vated, and the transition is from T
RS
to idle state. In
a pipelined cycle, both READY and ADS are active
and the transition is first from T
RS
state to T
P
state
then, after one clock period, back to T
RS
state.
3.4.4 BUSY AND PEREQ TIMING
RELATIONSHIP
Figure 3.7 shows the activation of BUSY at the be-
ginning of instruction execution and its deactivation
after execution of the instruction is complete. PER-
EQ is activated in this interval. If ERROR (not shown
in the diagram) is ever asserted, it would occur at
least six 386CLK2 periods after the deactivation of
PEREQ and at least six 386CLK2 periods before the
deactivation of BUSY. Figure 3.7 shows also that
STEN is activated at the beginning of a bus cycle.
271074–9
Cycle 1–Cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total.
The opcode write cycles and other overhead are not shown.
Note that the next cycle will be a pipelined cycle if both READY and ADS are sampled active at the end of a T
RS
state of the current cycle.
Figure 3.5. Fastest Transitions to and from Pipelined Cycles
27
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