參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 22/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
structions, decoding them, and sequencing the mi-
croinstructions, and for handling some of the admin-
istrative instructions. The BCL is responsible for i386
processor bus tracking and interface. The BCL is the
only unit in the i387 NPX that must run synchronous-
ly with the i386 processor; the rest of the i387 NPX
can run asynchronously with respect to the i386
processor.
3.2.1 BUS CONTROL LOGIC
The BCL communicates solely with the CPU using
I/O bus cycles. The BCL appears to the CPU as a
special peripheral device. It is special in two re-
spects: the CPU initiates I/O automatically when it
encounters ESC instructions, and the CPU uses re-
served I/O addresses to communicate with the BCL.
The BCL does not communicate directly with memo-
ry. The CPU performs all memory access, transfer-
ring input operands from memory to the i387 NPX
and transferring outputs from the i387 NPX to mem-
ory.
3.2.2 DATA INTERFACE AND CONTROL UNIT
The data interface and control unit latches the data
and, subject to BCL control, directs the data to the
FIFO or the instruction decoder. The instruction de-
coder decodes the ESC instructions sent to it by the
CPU and generates controls that direct the data flow
in the FIFO. It also triggers the microinstruction se-
quencer that controls execution of each instruction.
If the ESC instruction is FINIT, FCLEX, FSTSW,
FSTSW AX, or FSTCW, the control executes it inde-
pendently of the FPU and the sequencer. The data
interface and control unit is the one that generates
the BUSY, PEREQ and ERROR signals that syn-
chronize i387 NPX activities with the i386 processor.
It also supports the FPU in all operations that it can-
not perform alone (e.g. exceptions handling, tran-
scendental operations, etc.).
3.2.3 FLOATING POINT UNIT
The FPU executes all instructions that involve the
register stack, including arithmetic, logical, transcen-
dental, constant, and data transfer instructions. The
data path in the FPU is 84 bits wide (68 significant
bits, 15 exponent bits, and a sign bit) which allows
internal operand transfers to be performed at very
high speeds.
3.3 System Configuration
As an extension to the i386 processor, the i387 NPX
can be connected to the CPU as shown by Figure
3.2. A dedicated communication protocol makes
271074–6
Figure 3.2. i386
TM
/i387
TM
Processors System Configuration
22
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