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參數(shù)資料
| 型號： | intel i387 |
| 廠商： | Intel Corp. |
| 英文描述： | Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 457K |
| 代理商： | INTEL I387 |
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MILITARY i387
TM
MATH COPROCESSOR
Table 3.4. Bus Cycles Definition
STEN
NPS1
NPS2
CMD0
W/R
Bus Cycle Type
0
x
x
x
x
i387 NPX not selected and all
outputs in floating state
i387 NPX not selected
i387 NPX not selected
CW or SW read from i387 NPX
Opcode write to i387 NPX
Data read from i387 NPX
Data write to i387 NPX
1
1
1
1
1
1
1
x
0
0
0
0
x
0
1
1
1
1
x
x
0
0
1
1
x
x
0
1
0
1
possible high-speed transfer of opcodes and oper-
ands between the i386 microprocessor and i387
NPX. The i387 NPX is designed so that no additional
components are required for interface with the i386
processor. The i387 NPX shares the 32-bit wide lo-
cal bus of the i386 processor and most control pins
of the i387 NPX are connected directly to pins of the
i386 processor.
3.3.1 BUS CYCLE TRACKING
The ADS and READY signals allow the i387 NPX to
track the beginning and end of i386 processor bus
cycles, respectively. When ADS is asserted at the
same time as the i387 NPX chip-select inputs, the
bus cycle is intended for the i387 NPX. To signal the
end of a bus cycle for the i387 NPX, READY may be
asserted directly or indirectly by the i387 NPX or by
other bus-control logic. Refer to Table 3.4 for defini-
tion of the types of i387 NPX bus cycles.
3.3.2 i387
TM
NPX ADDRESSING
The NPS1, NPS2 and STEN signals allow the NPX
to identify which bus cycles are intended for the
NPX. The NPX responds only to I/O cycles when bit
31 of the I/O address is set. In other words, the NPX
acts as an I/O device in a reserved I/O address
space.
Because A
31
is used to select the i387 NPX for data
transfers, it is not possible for a program running on
the i386 processor to address the i387 NPX with an
I/O instruction. Only ESC instructions cause the
i386 processor to communicate with the i387 NPX.
The i386 processor BS16 input must be inactive dur-
ing I/O cycles when A
31
is active.
3.3.3 FUNCTION SELECTION
The CMD0 and W/R signals identify the four kinds of
bus cycle: control or status register read, data read,
opcode write, data write.
3.3.4 CPU/NPX Synchronization
The pin pairs BUSY, PEREQ, and ERROR are used
for various aspects of synchronization between the
CPU and the NPX.
BUSY is used to synchronize instruction transfer
from the i386 processor to the i387 NPX. When the
i387 NPX recognizes an ESC instruction, it asserts
BUSY. For most ESC instructions, the i386 proces-
sor waits for the i387 NPX to deassert BUSY before
sending the new opcode.
The NPX uses the PEREQ pin of the i386 CPU to
signal that the NPX is ready for data transfer to or
from its data FIFO. The NPX does not directly ac-
cess memory; rather, the i386 processor provides
memory access services for the NPX. Thus, memory
access on behalf of the NPX always obeys the rules
applicable to the mode of the i386 processor, wheth-
er the i386 processor be in real-address mode or
protected mode.
Once the i386 processor initiates an i387 NPX in-
struction that has operands, the i386 microproces-
sor waits for PEREQ signals that indicate when the
i387 NPX is ready for operand transfer. Once all op-
erands have been transferred (or if the instruction
has no operands) the i386 microprocessor contin-
ues program execution while the i387 NPX executes
the ESC instruction.
In M8086/M8087 systems, WAIT instructions may
be required to achieve synchronization of both com-
mands and operands. In M80286/M80287 and
i386/i387 processor systems, WAIT instructions are
required only for operand synchronization; namely,
after NPX stores to memory (except FSTSW and
FSTCW) or loads from memory. Used this way,
WAIT ensures that the value has already been writ-
ten or read by the NPX before the CPU reads or
changes the value.
Once it has started to execute a numerics instruction
and has transferred the operands from the i386
23
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