參數(shù)資料
型號： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學協(xié)處理器)
中文描述： 軍事I387數(shù)學協(xié)處理器（軍用I387數(shù)學協(xié)處理器）
文件頁數(shù)： 3/41頁
文件大?。?/td> 457K
代理商： INTEL I387
Military i387
TM
Math Coprocessor
CONTENTS
PAGE
1.0 FUNCTIONAL DESCRIPTION
ààààààààà 4
2.0 PROGRAMMING INTERFACE
ààààààààà 5
2.1 Data Types
àààààààààààààààààààààààààà 5
2.2 Numeric Operands
àààààààààààààààààà 5
2.3 Register Set
ààààààààààààààààààààààààà 7
2.3.1 Data Registers
àààààààààààààààààà 7
2.3.2 Tag Word
ààààààààààààààààààààààà 7
2.3.3 Status Word
àààààààààààààààààààà 8
2.3.4 Instruction and Data
Pointers
àààààààààààààààààààààààààà 11
2.3.5 Control Word
àààààààààààààààààà 13
2.4 Interrupt Description
àààààààààààààààà 13
2.5 Exception Handling
ààààààààààààààààà 14
2.6 Initialization
àààààààààààààààààààààààà 14
2.7 M8087 and M80287
Compatibility
ààààààààààààààààààààààààà 15
2.7.1 General Differences
ààààààààààà 15
2.7.2 Exceptions
àààààààààààààààààààà 16
3.0 HARDWARE INTERFACE
àààààààààààà 16
3.1 Signal Description
àààààààààààààààààà 16
3.1.1 M80386 Clock 2
(386CLK2)
àààààààààààààààààààààààà 20
3.1.2 M80387 Clock 2
(387CLK2)
àààààààààààààààààààààààà 20
3.1.3 M80387 Clocking Mode
(CKM)
àààààààààààààààààààààààààààà 20
3.1.4 System Reset (RESETIN)
àààààà 20
3.1.5 Processor Extension Request
(PEREQ)
ààààààààààààààààààààààààà 20
3.1.6 Busy Status (BUSY)
ààààààààààà 20
3.1.7 Error Status (ERROR)
ààààààààà 20
3.1.8 Data Pins (D31–D0)
ààààààààààà 21
3.1.9 Write/Read Bus Cycle
(W/R)
àààààààààààààààààààààààààààà 21
3.1.10 Address Strobe (ADS)
àààààààà 21
3.1.11 Bus Ready Input (READY)
àààà 21
CONTENTS
PAGE
3.1.12 Ready Output (READYO)
ààààà 21
3.1.13 Status Enable (STEN)
àààààààà 21
3.1.14 NPX Select
Y
1 (NPS1)
ààààààà 21
3.1.15 NPX Select
Y
2 (NPS2)
ààààààà 21
3.1.16 Command (CMD0)
ààààààààààà 21
3.2 Processor Architecture
ààààààààààààà 21
3.2.1 Bus Control Logic
àààààààààààààà 22
3.2.2 Data Interface and Control
Unit
ààààààààààààààààààààààààààààààà 22
3.2.3 Floating Point Unit
ààààààààààààà 22
3.3 System Configuration
ààààààààààààààà 22
3.3.1 Bus Cycle Tracking
àààààààààààà 23
3.3.2 i387
TM
NPX Addressing
àààààààà 23
3.3.3 Function Selection
ààààààààààààà 23
3.3.4 CPU/NPX Synchronization
àààà 23
3.3.5 Synchronous or
Asynchronous Modes
ààààààààààààà 24
3.3.6 Automatic Bus Cycle
Termination
ààààààààààààààààààààààà 24
3.4 Bus Operation
àààààààààààààààààààààà 24
3.4.1 Nonpipelined Bus Cycles
àààààà 25
3.4.1.1 Write Cycle
ààààààààààààààà 25
3.4.1.2 Read Cycle
ààààààààààààààà 25
3.4.2 Pipelined Bus Cycles
àààààààààà 26
3.4.3 Bus Cycles of Mixed Type
ààààà 27
3.4.4 BUSY and PEREQ Timing
Relationship
àààààààààààààààààààààà 27
5.0 ELECTRICAL DATA
àààààààààààààààààà 29
5.1 Absolute Maximum Ratings
ààààààààà 29
5.2 DC Characteristics
ààààààààààààààààà 30
5.3 AC Characteristics
àààààààààààààààààà 31
6.0 i387
TM
NUMERICS COPROCESSOR
EXTENSIONS TO THE i386
TM
MICROPROCESSOR INSTRUCTION
SET
àààààààààààààààààààààààààààààààààààà 36
APPENDIX A
àààààààààààààààààààààààààààà A-1
3
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