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參數(shù)資料
| 型號： | intel i387 |
| 廠商： | Intel Corp. |
| 英文描述： | Military I387 Math Coprocessor(軍用I387數(shù)學協(xié)處理器) |
| 中文描述： | 軍事I387數(shù)學協(xié)處理器（軍用I387數(shù)學協(xié)處理器） |
| 文件頁數(shù)： | 11/41頁 |
| 文件大小： | 457K |
| 代理商： | INTEL I387 |
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MILITARY i387
TM
MATH COPROCESSOR
2.3.4 INSTRUCTION AND DATA POINTERS
Because the NPX operates in parallel with the CPU,
any errors detected by the NPX may be reported
after the CPU has executed the ESC instruction
which caused it. To allow identification of the failing
numeric instruction, the i386/i387 processor combi-
nation contains two pointer registers that supply the
address of the failing numeric instruction and the ad-
dress of its numeric memory operand (if appropri-
ate).
The instruction and data pointers are provided for
user-written error handlers. These registers are ac-
tually located in the i386 microprocessor, but appear
to be located in the i387 NPX because they are ac-
cessed by the ESC instructions FLDENV, FSTENV,
FSAVE, and FRSTOR. (In the M8086/M8087 and
M80286/M80287, these registers are located in
the NPX.) Whenever the i386 processor decodes a
new ESC instruction, it saves the address of the in-
struction (including any prefixes that may be pres-
ent), the address of the operand (if present), and the
opcode.
The instruction and data pointers appear in one of
four formats depending on the operating mode of
the i386 processor (protected mode or real-address
mode) and depending on the operand-size attribute
in effect (32-bit operand or 16-bit operand). When
the i386 microprocessor is in virtual-M8086 mode,
the real-address mode formats are used. (See Fig-
ures
2.3
through
2.6.)
FLDENV, FSTENV, FSAVE, and FRSTOR are used
to transfer these values between the M80386 regis-
ters and memory. Note that the value of the data
pointer is undefined if the prior ESC instruction did
not have a memory operand.
The
ESC
instructions
32-BIT PROTECTED MODE FORMAT
15
31
23
7
0
RESERVED
CONTROL WORD
0
RESERVED
STATUS WORD
4
RESERVED
TAG WORD
8
IP OFFSET
C
00000
OPCODE 10..0
CS SELECTOR
10
DATA OPERAND OFFSET
14
RESERVED
OPERAND SELECTOR
18
Figure 2.3. Protected Mode i387
TM
NPX Instruction and Data Pointer Image in Memory, 32-Bit Format
11
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