參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 24/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
processor, the i387 NPX can process the instruction
in parallel with and independent of the host CPU.
When the NPX detects an exception, it asserts the
ERROR signal, which causes an i386 processor in-
terrupt.
3.3.5 SYNCHRONOUS OR ASYNCHRONOUS
MODES
The internal logic of the i387 NPX (the FPU) can
either operate directly from the CPU clock (synchro-
nous mode) or from a separate clock (asynchronous
mode). The two configurations are distinguished by
the CKM pin. In either case, the bus control logic
(BCL) of the i387 NPX is synchronized with the CPU
clock. Use of asynchronous mode allows the i386
microprocessor and the FPU section of the i387
NPX to run at different speeds. In this case, the ratio
of the frequency of 387CLK2 to the frequency of
386CLK2 must lie within the range 10:16 to 16:10.
Use of synchronous mode eliminates one clock gen-
erator from the board design.
3.3.6 AUTOMATIC BUS CYCLE TERMINATION
In configurations where no extra wait states are re-
quired, READYO can be used to drive the i386 mi-
croprocessor READY input. If this pin is used, it
should be connected to the logic that ORs all
READY outputs from peripherals on the i386 micro-
processor bus. READYO is asserted by the i387
NPX only during I/O cycles that select the i387 NPX.
Refer to section 3.4 ‘‘Bus Operation’’ for details.
3.4 Bus Operation
With respect to the bus interface, the i387 NPX is
fully synchronous with the i386 processor. Both op-
erate at the same rate, because each generates its
internal CLK signal by dividing 386CLK2 by two.
The i386 processor initiates a new bus cycle by acti-
vating ADS. The i387 NPX recognizes a bus cycle, if,
during the cycle in which ADS is activated, STEN,
NPS1, and NPS2 are all activated. Proper operation
is achieved if NPS1 is connected to the M/IO output
of the i386 processor, and NPS2 to the A31 output.
The i386 processor’s A31 output is guaranteed to be
inactive in all bus cycles that do not address the i387
NPX (i.e. I/O cycles to other devices, interrupt ac-
knowledge, and reserved types of bus cycles). Sys-
tem logic must not signal a 16-bit bus cycle via the
i386 processor BS16 input during I/O cycles when
A31 is active.
During the CLK period in which ADS is activated, the
i387 NPX also examines the W/R input signal to de-
termine whether the cycle is a read or a write cycle
and
examines
the
CMD0
input
to
determine
whether an opcode, operand, or control/status reg-
ister transfer is to occur.
The i387 NPX supports both pipelined and nonpipe-
lined bus cycles. A nonpipelined cycle is one for
which the i386 processor asserts ADS when no oth-
er i387 NPX bus cycle is in progress. A pipelined bus
cycle is one for which the i386 processor asserts
ADS and provides valid next-address and control
signals as soon as in the second CLK period after
the ADS assertion for the previous i386 processor
bus cycle. Pipelining increases the availability of the
bus by at least one CLK period. The i387 NPX sup-
ports pipelined bus cycles in order to optimize ad-
dress pipelining by the i386 processor for memory
cycles.
Bus operation is described in terms of an abstract
state machine. Figure 3.3 illustrates the states and
state transitions for i387 NPX bus cycles:
#
T
I
is the idle state. This is the state of the bus
logic after RESET, the state to which bus logic
returns after evey nonpipelined bus cycle, and
the state to which bus logic returns after a series
of pipelined cycles.
#
T
RS
is the READY sensitive state. Different types
of bus cycle may require a minimum of one or two
successive T
RS
states. The bus logic remains in
T
RS
state until READY is sensed, at which point
the bus cycle terminates. Any number of wait
states may be implemented by delaying READY,
thereby
causing
additional
states.
#
T
P
is the first state for every pipelined bus cycle.
successive
T
RS
The READYO output of the i387 NPX indicates
when a bus cycle for the i387 NPX may be terminat-
ed if no extra wait states are required. For all write
cycles (except those for the instructions FLDENV
and
FRSTOR),
READYO
is
always
assert-
271074–7
Figure 3.3. Bus State Diagram
24
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