參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 14/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
Table 2.6. i386
TM
Microprocessor Interrupt Vectors Reserved for NPX
Interrupt
Number
Cause of Interrupt
7
An ESC instruction was encountered when EM or TS of i386 processor control register
zero (CR0) was set. EM
e
1 indicates that software emulation of the instruction is
required. When TS is set, either an ESC or WAIT instruction causes interrupt 7. This
indicates that the current NPX context may not belong to the current task.
9
An operand of a coprocessor instruction wrapped around an addressing limit (0FFFFH for
small segments, 0FFFFFFFFH for big segments, zero for expand-down segments) and
spanned inaccessible addresses
a
. The failing numerics instruction is not restartable. The
address of the failing numerics instruction and data operand may be lost; an FSTENV does
not return reliable addresses. As with the M80286/M80287, the segment overrun
exception should be handled by executing an FNINIT instruction (i.e. an FINIT without a
preceding WAIT). The return address on the stack does not necessarily point to the failing
instruction nor to the following instruction. The interrupt can be avoided by never allowing
numeric data to start within 108 bytes of the end of a segment.
13
The first word or doubleword of a numeric operand is not entirely within the limit of its
segment. The return address pushed onto the stack of the exception handler points at the
ESC instruction that caused the exception, including any prefixes. The M80387 has not
executed this instruction; the instruction pointer and data pointer register refer to a
previous, correctly executed instruction.
16
The previous numerics instruction caused an unmasked exception. The address of the
faulty instruction and the address of its operand are stored in the instruction pointer and
data pointer registers. Only ESC and WAIT instructions can cause this interrupt. The
M80386 return address pushed onto the stack of the exception handler points to a WAIT
or ESC instruction (including prefixes). This instruction can be restarted after clearing the
exception condition in the NPX. FNINIT, FNCLEX, FNSTSW, FNSTENV, and FNSAVE
cannot cause this interrupt.
a.
An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid
address in the segment. Because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the
segment. There are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing
limit (e.g. addressing limit is FFFFH and segment limit is FFFDH) the operand will span addresses that are not within the segment (e.g. an 8-byte
operand that starts at valid offset FFFC will span addresses FFFC–FFFF and 0000-0003; however addresses FFFE and FFFF are not valid,
because they exceed the limit); 2) if the operand begins and ends in present and accessible pages but intermediate bytes of the operand fall in a
not-present page or a page to which the procedure does not have access rights.
2.5 Exception Handling
The i387 NPX detects six different exception condi-
tions that can occur during instruction execution. Ta-
ble 2.7 lists the exception conditions in order of
precedence, showing for each the cause and the
default action taken by the i387 NPX if the exception
is masked by its corresponding mask bit in the con-
trol word.
Any exception that is not masked by the control
word sets the corresponding exception flag of the
status word, sets the ES bit of the status word, and
asserts the ERROR signal. When the CPU attempts
to execute another ESC instruction or WAIT, excep-
tion 16 occurs. The exception condition must be re-
solved via an interrupt service routine. The i386/i387
processor combination saves the address of the
floating-point instruction that caused the exception
and the address of any memory operand required by
that instruction.
2.6 Initialization
i387 NPX initialization software must execute an
FNINIT instruction (i.e. an FINIT without a preceding
WAIT) to clear ERROR. The FNINIT is not required
for the M80287, though Intel documentation recom-
mends its use (refer to the Numerics Supplement to
the80286 Programmer’s Reference Manual). After a
hardware RESET, the ERROR output is asserted to
indicate that an M80387 is present. To accomplish
this, the IE and ES bits of the status word are set,
and the IM bit in the control word is reset. After
FNINIT, the status word and the control word have
the same values as in an M80287 after RESET.
14
相關(guān)PDF資料
PDF描述
intel M80C186 CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器)
intel Pentium CPU 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動(dòng)模塊處理器)
intel Pentium II processor Pentium II Processor Mobile Module(帶移動(dòng)模塊奔II處理器)
INTEL386 CXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
INTEL386 CXSB Low-Voltage, 32-Bit, Fully Static Embedded Microprocessor(低電壓32位完全靜態(tài)嵌入式微處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTELLIGENT CHARGER + 4AA 制造商:Energizer 功能描述:Bulk
INTELLI-INCH-LR-STARTER K 制造商:ALL MOTION 功能描述:Intelli-Inch Stepper & Controller Starter Kit
INTELLIPANEL 制造商:GJD 功能描述:EXTENSION LEAD 8GANG INTELLIPANEL 制造商:GJD 功能描述:EXTENSION LEAD, 8GANG, INTELLIPANEL
INTELLIPLUG 制造商:GLOBAL COMMUNICATIONS 功能描述:ADAPTOR 3WAY INTELLIPLUG
INTELLIPROBE 100 制造商:Fluke Networks 功能描述:TONE + PROBE KIT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*