- 您現在的位置：買賣IC網 > PDF目錄377495 > intel i387 (Intel Corp.) Military I387 Math Coprocessor(軍用I387數學協(xié)處理器) PDF資料下載
參數資料
| 型號： | intel i387 |
| 廠商： | Intel Corp. |
| 英文描述： | Military I387 Math Coprocessor(軍用I387數學協(xié)處理器) |
| 中文描述： | 軍事I387數學協(xié)處理器（軍用I387數學協(xié)處理器） |
| 文件頁數： | 26/41頁 |
| 文件大?。?/td> | 457K |
| 代理商： | INTEL I387 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
MILITARY i387
TM
MATH COPROCESSOR
271074–8
Cycles 1 & 2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads.
Cycles 3 & 4 represent part of the operand transfer cycle for a store operation.
*
Cycles 1 & 2 could repeat here or T
I
states for various non-operand transfer cycles and overhead.
Figure 3.4. Nonpipelined Read and Write Cycles
3.4.2 PIPELINED BUS CYCLES
Because all the activities of the i387 NPX bus inter-
face occur either during the T
RS
state or during the
transitions to or from that state, the only difference
between a pipelined and a nonpipelined cycle is the
manner of changing from one state to another. The
exact activities in each state are detailed in the pre-
vious section ‘‘Nonpipelined Bus Cycles’’.
When the i386 processor asserts ADS before the
end of a bus cycle, both ADS and READY are active
during a T
RS
state. This condition causes the i387
NPX to change to a different state named T
P
. The
i387 NPX activities in the transition from a T
RS
state
to a T
P
state are exactly the same as those in the
transition from a T
RS
state to a T
I
state in non-
pipelined cycles. T
P
state is metastable; therefore,
one clock period later the i387 NPX returns to T
RS
state. In consecutive pipelined cycles, the i387 NPX
bus logic uses only T
RS
and T
P
states.
Figure 3.5 shows the fastest transition into and out
of the pipelined bus cycles. Cycle 1 in this figure
represents a nonpipelined cycle. (Nonpipelined write
cycles with only one T
RS
state (i.e. no wait states)
are always followed by another nonpipelined cycle,
because READY is asserted before the earliest pos-
sible assertion of ADS for the next cycle.)
Figure 3.6 shows the pipelined write and read cycles
with one additional T
RS
states beyond the minimum
required. To delay the assertion of READY requires
external logic.
26
相關PDF資料 |
PDF描述 |
|---|---|
| intel M80C186 | CHMOS High Integration 16-Bit Microprocessor(CHMOS 高集成16位微處理器) |
| intel Pentium CPU | 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動模塊處理器) |
| intel Pentium II processor | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| INTEL386 CXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| INTEL386 CXSB | Low-Voltage, 32-Bit, Fully Static Embedded Microprocessor(低電壓32位完全靜態(tài)嵌入式微處理器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
| INTELLI-INCH-LR-STARTER K | 制造商:ALL MOTION 功能描述:Intelli-Inch Stepper & Controller Starter Kit |
| INTELLIPANEL | 制造商:GJD 功能描述:EXTENSION LEAD 8GANG INTELLIPANEL 制造商:GJD 功能描述:EXTENSION LEAD, 8GANG, INTELLIPANEL |
| INTELLIPLUG | 制造商:GLOBAL COMMUNICATIONS 功能描述:ADAPTOR 3WAY INTELLIPLUG |
| INTELLIPROBE 100 | 制造商:Fluke Networks 功能描述:TONE + PROBE KIT |
發(fā)布緊急采購，3分鐘左右您將得到回復。