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| 型號： | intel i387 |
| 廠商： | Intel Corp. |
| 英文描述： | Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 16/41頁 |
| 文件大小： | 457K |
| 代理商： | INTEL I387 |
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MILITARY i387
TM
MATH COPROCESSOR
2.7.2 EXCEPTIONS
A number of differences exist due to changes in the
IEEE standard and to functional improvements to
the architecture of the M80387:
1. When the overflow or underflow exception is
masked, the i387 NPX differs from the M80287
in rounding when overflow or underflow occurs.
The i387 NPX produces results that are consist-
ent with the rounding mode.
2. When the underflow exception is masked, the
i387 NPX sets its underflow flag only if there is
also a loss of accuracy during denormalization.
3. Fewer invalid-operation exceptions due to de-
normal
operands,
because
FSQRT, FDIV, FPREM, and conversions to BCD
or to integer normalize denormal operands be-
fore proceeding.
the
instructions
4. The FSQRT, FBSTP, and FPREM instructions
may cause underflow, because they support de-
normal operands.
5. The denormal exception can occur during the
transcendental instructions and the FXTRACT
instruction.
6. The denormal exception no longer takes prece-
dence over all other exceptions.
7. When the denormal exception is masked, the
i387 NPX automatically normalizes denormal op-
erands. The M8087/M80287 performs unnormal
arithmetic, which might produce an unnormal re-
sult.
8. When the operand is zero, the FXTRACT in-
struction reports a zero-divide exception and
leaves
b
%
in ST(1).
9. The status word has a new bit (SF) that signals
when invalid-operation exceptions are due to
stack underflow or overflow.
10. FLDextended precision no longer reports denor-
mal exceptions, because the instruction is not
numeric.
11. FLD single/double precision when the operand
is denormal converts the number to extended
precision and signals the denormalized operand
exception. When loading a signaling NaN, FLD
single/double precision signals an invalid-oper-
and exception.
12. The i387 NPX only generates quiet NaNs (as on
the M80287); however, the i387 NPX distin-
guishes between quiet NaNs and signaling
NaNs. Signaling NaNs trigger exceptions when
they are used as operands; quiet NaNs do not
(except for FCOM, FIST, and FBSTP which also
raise IE for quiet NaNs).
13. When stack overflow occurs during FPTAN and
overflow is masked, both ST(0) and ST(1) con-
tain quiet NaNs. The M80287/M8087 leaves the
original operand in ST(1) intact.
14. When the scaling factor is
g
%
, the FSCALE
(ST(0), ST(1)) instruction behaves as follows
(ST(0) and ST(1) contain the scaled and scaling
operands respectively):
#
FSCALE(0,
%
) generates the invalid operation
exception.
#
FSCALE(finite,
b
%
) generates zero with the
same sign as the scaled operand.
#
FSCALE(finite,
a
%
) generates
%
with the
same sign as the scaled operand.
The M8087/M80287 returns zero in the first
case and raises the invalid-operation exception
in the other cases.
15. The i387 NPX returns signed infinity/zero as the
unmasked response to massive overflow/under-
flow. The M8087 and M80287 support a limited
range for the scaling factor; within this range ei-
ther massive overflow/underflow do not occur or
undefined results are produced.
3.0 HARDWARE INTERFACE
3.1 Signal Description
In the following signal descriptions, the i387 coproc-
essor pins are grouped by function as follows:
1. Execution controlD386CLK2, 387CLK2, CKM,
RESETIN
2. NPX handshakeDPEREQ, BUSY, ERROR
3. Bus interface pinsDD31–D0, W/R, ADS, READY,
READYO
4. Chip/Port SelectDSTEN, NPS1, NPS2, CMD0
5. Power suppliesDV
CC
, V
SS
Table 3.1 lists every pin by its identifier, gives a brief
description of its function, and lists some of its char-
acteristics. All output signals are tristate; they leave
floating state only when STEN is active. The output
buffers of the bidirectional data pins D31–D0 are
also tristate; they leave floating state only in read
cycles when the i387 NPX is selected (i.e. when
STEN, NPS1, and NPS2 are all active).
Figure 3.1 and Table 3.2 together show the location
of every pin in the pin grid array.
16
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