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參數資料
| 型號： | intel i387 |
| 廠商： | Intel Corp. |
| 英文描述： | Military I387 Math Coprocessor(軍用I387數學協(xié)處理器) |
| 中文描述： | 軍事I387數學協(xié)處理器（軍用I387數學協(xié)處理器） |
| 文件頁數： | 21/41頁 |
| 文件大?。?/td> | 457K |
| 代理商： | INTEL I387 |
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MILITARY i387
TM
MATH COPROCESSOR
3.1.8 DATA PINS (D31–D0)
These bidirectional pins are used to transfer data
and opcodes between the i386 microprocessor and
i387 NPX. They are normally connected directly to
the corresponding i386 processor data pins. HIGH
state indicates a value of one. D0 is the least signifi-
cant data bit. Timings are referenced to 386CLK2.
3.1.9 WRITE/READ BUS CYCLE (W/R)
This signal indicates to the i387 NPX whether the
i386 processor bus cycle in progress is a read or a
write cycle. This pin should be connected directly to
the i386 processor W/R pin. HIGH indicates a write
cycle; LOW, a read cycle. This input is ignored if any
of the signals STEN, NPS1, or NPS2 is inactive. Set-
up and hold times are referenced to 386CLK2.
3.1.10 ADDRESS STROBE (ADS)
This input, in conjunction with the READY input indi-
cates when the i387 NPX bus-control logic may
sample W/R and the chip-select signals. Setup and
hold times are referenced to 386CLK2. This pin
should be connected to the i386 processor ADS pin.
3.1.11 BUS READY INPUT (READY)
This input indicates to the i387 NPX when an i386
processor bus cycle is to be terminated. It is used by
the bus-control logic to trace bus activities. Bus cy-
cles can be extended indefinitely until terminated by
READY. This input should be connected to the same
signal that drives the i386 processor READ input.
Setup and hold times are referenced to 386CLK2.
3.1.12 READY OUTPUT (READYO)
This pin is activated at such a time that write cycles
are terminated after two clocks and read cycles after
three clocks. In configurations where no extra wait
states are required, it can be used to directly drive
the i386 processor READY input. Refer to section
3.4 ‘‘Bus Operation’’ for details. This pin is activated
only during bus cycles that select the i387 NPX. This
signal is referenced to 386CLK2.
3.1.13 STATUS ENABLE (STEN)
This pin serves as a chip select for the i387 NPX.
When inactive, this pin forces BUSY, PEREQ,
ERROR, and READYO outputs into floating state.
D31–D0 are normally floating and leave floating
state only if STEN is active and additional conditions
are met. STEN also causes the chip to recognize its
other chip-select inputs. STEN makes it easier to do
on-board testing (using the overdrive method) of
other chips in systems containing the i387 NPX.
STEN should be pulled up with a resistor so that it
can be pulled down when testing. In boards that do
not use on-board testing, STEN should be connect-
ed to V
CC
. Setup and hold times are relative to
386CLK2. Note that STEN must maintain the same
setup and hold times as NPS1, NPS2, and CMD0
(i.e. if STEN changes state during an M80387 bus
cycle, it should change state during the same CLK
period as the NPS1, NPS2, and CMD0 signals).
3.1.14 NPX SELECT
Y
1 (NPS1)
When active (along with STEN and NPS2) in the first
period of an i386 microprocessor bus cycle, this sig-
nal indicates that the purpose of the bus cycle is to
communicate with the i387 NPX. This pin should be
connected directly to the i386 processor M/IO pin,
so that the i387 NPX is selected only when the
M80386 performs I/O cycles. Setup and hold times
are referenced to 386CLK2.
3.1.15 NPX SELECT
Y
2 (NPS2)
When active (along with STEN and NPS1) in the first
period of an i386 processor bus cycle, this signal
indicates that the purpose of the bus cycle is to com-
municate with the i387 NPX. This pin should be con-
nected directly to the i386 microprocessor A31 pin,
so that the i387 NPX is selected only when the i386
processor uses one of the I/O addresses reserved
for the i387 NPX (800000F8 or 800000FC). Setup
and hold times are referenced to 386CLK2.
3.1.16 COMMAND (CMD0)
During a write cycle, this signal indicates whether an
opcode (CMD0 active) or data (CMD0 inactive) is
being sent to the i387 NPX. During a read cycle, it
indicates whether the control or status register
(CMD0 active) or a data register (CMD0 inactive) is
being read. CMD0 should be connected directly to
the A2 output of the i386 microprocessor. Setup and
hold times are referenced to 386CLK2.
3.2 Processor Architecture
As shown by the block diagram on the front page,
the NPX is internally divided into three sections: the
bus control logic (BCL), the data interface and con-
trol unit, and the floating point unit (FPU). The FPU
(with the support of the control unit which contains
the sequencer and other support units) executes all
numerics instructions. The data interface and control
unit is responsible for the data flow to and from the
FPU and the control registers, for receiving the in-
21
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