參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 25/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
ed in the first T
RS
state, regardless of the number of
wait states. For all read cycles and write cycles for
FLDENV and FRSTOR, READYO is always asserted
in the second T
RS
state, regardless of the number of
wait states. These rules apply to both pipelined and
nonpipelined cycles. Systems designers may use
READYO in one of three ways:
1. Leave it disconnected and use external logic to
generate READY signals. When choosing this op-
tion, i387 NPX requirements for wait states in read
cycles and write cycles of FLDENV and FRSTOR
must be obeyed.
2. Connect it (directly or through logic that ORs
READY signals from other devices) to the READY
inputs of the i386 processor and i387 NPX.
3. Use it as one input to a wait-state generator.
The following sections illustrate different types of
i387 NPX bus cycles.
Because
amounts of overhead before, between, and after op-
erand transfer cycles, it is not possible to represent
in a few diagrams all of the combinations of succes-
sive operand transfer cycles. The following bus-cy-
cle diagrams show memory cycles between i387
NPX operand-transfer cycles. Note however that,
during the instructions FLDENV, FSTENV, FSAVE,
and FRSTOR, some consecutive accesses to the
NPX do not have intervening memory accesses. For
the timing relationship between operand transfer cy-
cles and opcode write or other overhead activities,
see Figure 3.7.
different
instructions
have
different
3.4.1 NONPIPELINED BUS CYCLES
Figure 3.4 illustrates bus activity for consecutive
nonpipelined bus cycles.
3.4.1.1 Write Cycle
At the second clock of the bus cycle, the M80387
enters the T
RS
(READY-sensitive) state. During this
state, the i387 NPX samples the READY input and
stays in this state as long as READY is inactive.
In write cycles, the i387 NPX drives the READYO
signal for one CLK period beginning with the second
CLK of the bus cycle; therefore, the fastest write
cycle takes two CLK cycles (see cycle 2 of Figure
3.4). For the instructions FLDENV and FRSTOR,
however, the i387 NPX forces a wait state by delay-
ing the activation of READYO to the second T
RS
cycle (not shown in Figure 3.4).
When READY is asserted the M80387 returns to the
idle state, in which ADS could be asserted again by
the i386 processor for the next cycle.
3.4.1.2 Read Cycle
At the second clock of the bus cycle, the i387 NPX
enters the T
RS
state. See Figure 3.4. In this state,
the i387 NPX samples the READY input and stays in
this state as long as READY is inactive.
At the rising edge of CLK in the second clock period
of the cycle, the i387 NPX starts to drive the D31–
D0 outputs and continues to drive them as long as it
stays in T
RS
state.
In read cycles that address the i387 NPX, at least
one wait state must be inserted to insure that the
i386 microprocessor latches the correct data. Since
the i387 NPX starts driving the system data bus only
at the rising edge of CLK in the second clock period
of the bus cycle, not enough time is left for the data
signals to propagate and be latched by the i386
processor at the falling edge of the same clock peri-
od. The i387 NPX drives the READYO signal for one
CLK period in the third CLK of the bus cycle. There-
fore, if the READYO output is used to drive the i386
processor READY input, one wait state is inserted
automatically.
Because one wait state is required for i387 NPX
reads, the minimum is three CLK cycles per read, as
cycle 3 of Figure 3.4 shows.
When READY is asserted the i387 NPX returns to
the idle state, in which ADS could be asserted again
by the i386 processor for the next cycle. The tran-
sition from T
RS
state to idle state causes the i387
NPX to put the tristate D31–D0 outputs into the
floating state, allowing another device to drive the
system data bus.
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