參數(shù)資料
型號(hào)： intel i387
廠商： Intel Corp.
英文描述： Military I387 Math Coprocessor(軍用I387數(shù)學(xué)協(xié)處理器)
中文描述： 軍事I387數(shù)學(xué)協(xié)處理器（軍用I387數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 20/41頁(yè)
文件大?。?/td> 457K
代理商： INTEL I387
MILITARY i387
TM
MATH COPROCESSOR
3.1.1 M80386 CLOCK 2 (386CLK2)
This input uses the M80386 CLK2 signal to time the
bus control logic. Several other M80387 signals are
referenced to the rising edge of this signal. When
CKM
e
1 (synchronous mode) this pin also clocks
the data interface and control unit and the floating-
point unit of the M80387. This pin requires MOS-lev-
el input. The signal on this pin is divided by two to
produce the internal clock signal CLK.
3.1.2 M80387 CLOCK 2 (387CLK2)
When CKM
e
0 (asynchronous mode) this pin pro-
vides the clock for the data interface and control unit
and the floating-point unit of the M80387. In this
case, the ratio of the frequency of 387CLK2 to the
frequency of 386CLK2 must lie within the range
10:16 to 14:10. When CKM
e
1 (synchronous
mode) this pin is ignored; 386CLK2 is used instead
for the data interface and control unit and the float-
ing-point unit. This pin requires TTL-level input.
3.1.3 M80387 CLOCKING MODE (CKM)
This pin is a strapping option. When it is strapped to
V
CC
, the i387 NPX operates in synchronous mode;
when strapped to V
SS
, the i387 NPX operates in
asynchronous mode. These modes relate to clock-
ing of the data interface and control unit and the
floating-point unit only; the bus control logic always
operates synchronously with respect to the i386
processor.
3.1.4 SYSTEM RESET (RESETIN)
A LOW to HIGH transition on this pin causes the
i387 NPX to terminate its present activity and to en-
ter a dormant state. RESETIN must remain HIGH for
at least 40 387CLK2 periods. The HIGH to LOW
transitions of RESETIN must be synchronous with
386CLK2, so that the phase of the internal clock of
the bus control logic (which is the 386CLK2 divided
by 2) is the same as the phase of the internal clock
of the i386 microprocessor. After RESETIN goes
LOW, at least 50 387CLK2 periods must pass before
the first NPX instruction is written into the i387 co-
processor. This pin should be connected to the i386
microprocessor RESET pin. Table 3.3 shows the
status of other pins after a reset.
Table 3.3. Output Pin Status during Reset
Pin Value
Pin Name
HIGH
READYO, BUSY
LOW
PEREQ, ERROR
Tri-State OFF
D31–D0
3.1.5 PROCESSOR EXTENSION REQUEST
(PEREQ)
When active, this pin signals to the i386 CPU that
the i387 NPX is ready for data transfer to/from its
data FIFO. When all data is written to or read from
the data FIFO, PEREQ is deactivated. This signal
always goes inactive before BUSY goes inactive.
This signal is referenced to 386CLK2. It should be
connected to the i386 microprocessor PEREQ input.
Refer to Figure 3.7 for the timing relationships be-
tween this and the BUSY and ERROR pins.
3.1.6 BUSY STATUS (BUSY)
When active, this pin signals to the i386 CPU that
the i387 NPX is currently executing an instruction.
This signal is referenced to 386CLK2. It should be
connected to the i386 microprocessor BUSY pin.
Refer to Figure 3.7 for the timing relationships be-
tween this and the PEREQ and ERROR pins.
3.1.7 ERROR STATUS (ERROR)
This pin reflects the ES bits of the status register.
When active, it indicates that an unmasked excep-
tion has occurred (except that, immediately after a
reset, it indicates to the i386 microprocessor that an
i387 NPX is present in the system). This signal can
be changed to inactive state only by the following
instructions (without a preceding WAIT): FNINIT,
FNCLEX, FNSTENV, and FNSAVE. This signal is
referenced to 387CLK2. It should be connected to
the i386 microprocessor ERROR pin. Refer to Fig-
ure 3.7 for the timing relationships between this and
the PEREQ and BUSY pins.
20
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